CDR Built-In Self-Test Circuit for Jitter Phase Measurement
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Solution Overview
Problem
The performance of Clock and Data Recovery (CDR) circuits is degraded due to unacceptable dithering in digital codes, leading to significant jitter in recovery clocks, which is a challenge in high-speed serial communication systems.
Innovation Solution
A Built-In Self-Test (BIST) circuit is introduced to measure the performance of CDR circuits by varying the phase of input data, utilizing a delay controller and a CDR performance monitoring circuit to adjust the phase of the clock signal and evaluate recovery performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a CDR circuit is used to detect phase and generate recovery clocks from serial data, then high-speed data transmission is enabled, but dithering in digital codes causes jitter in recovery clocks degrading performance
Solution Approach 1:
The CDR circuit performs self-diagnosis by monitoring its own digital codes through a monitoring unit. The circuit automatically detects dithering phenomena and identifies problematic phase interpolation codes without external intervention, enabling self-service performance optimization.
Solution Approach 2:
The monitoring unit continuously observes digital codes from the CDR circuit and feeds back information about dithering patterns. This feedback mechanism allows the system to identify codes causing excessive jitter and adjust operations to maintain optimal performance.
2Measurement precision
If the phase of input data is varied to measure CDR performance, then comprehensive performance measurement is achieved, but system complexity increases
Solution Approach 1:
The BIST circuit merges the test signal generation, phase variation, and performance monitoring functions into a single integrated unit. The delay controller and monitoring unit work together within the BIST framework to vary input phase and measure CDR performance simultaneously, reducing overall system complexity.
Solution Approach 2:
The BIST circuit serves multiple functions: it generates test patterns, varies input phase through delay control, monitors digital codes, and evaluates CDR performance. This multi-functional design eliminates the need for separate external test equipment for each measurement function.
Data Source
AI summary
A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.