Combined CDR Logic and Charge Pump for Low-Latency DFE
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Solution Overview
Problem
High-speed communications systems face challenges in achieving accurate clock data recovery and data-dependent equalization at high data rates due to limitations in sampling rates and power utilization, with conventional methods struggling to compute Decision Feedback Equalization (DFE) compensation in time for next data samples, leading to increased latency and receiver complexity.
Innovation Solution
A multi-phase speculative DFE system that uses a sequence of data decisions and error signals to select logic branches, generating output currents to adjust the input voltage of a proportional control circuit, allowing for improved clock recovery and reduced latency through the use of a combined logic network and charge pump circuit, enabling efficient clock data recovery and equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If receive sampling is performed at twice the expected data reception rate to enable independent detection of data component and clock component, then clock data recovery capability is improved, but receiver power utilization substantially increases
Solution Approach 1:
The patent segments the receive sampling process into two distinct modes: double-baud-rate sampling for clock data recovery operations and single-baud-rate sampling for normal data reception. The system dynamically switches between these modes based on operational requirements, allowing high-precision clock recovery when needed while reducing power consumption during standard data transmission by using the lower sampling rate.
2Measurement precision
If DFE compensation is computed explicitly before next data sample detection, then equalization accuracy is improved, but computation time becomes insufficient at higher data rates
Solution Approach 1:
The patent implements preliminary computation of DFE compensation values by pre-calculating compensation for multiple speculative data bit scenarios (0 and 1) in advance. These pre-computed compensation values are stored and ready for immediate use when the actual data bit is detected, eliminating the need for time-consuming computations during the critical sampling window and enabling high-speed operation without sacrificing equalization accuracy.
3Productivity
If unrolled DFE computations are performed on speculative data values, then computation speed is improved, but receiver complexity increases
Solution Approach 1:
The patent employs dynamic speculative computation where the receiver performs DFE compensation calculations for both possible data bit values (0 and 1) simultaneously, then selectively applies the correct compensation based on the actual detected data bit. This dynamic approach allows the system to maintain simplified computation paths while achieving high-speed processing, as only one of the two speculative computations needs to be fully executed and applied at any given time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the effective PLL loop bandwidth, reduces latency, and improves clock noise immunity by allowing for direct CDR feedback from data decisions and error signals, effectively addressing the limitations of conventional methods at high data rates.
Implementation Method 1
A multi-phase speculative DFE system that uses a sequence of data decisions and error signals to select logic branches, generating output currents to adjust the input voltage of a proportional control circuit
Data Source
AI summary
Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.