Clock Data Recovery Circuit With Dual-Cycle Phase Summing
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Solution Overview
Problem
Existing clock and data recovery systems face challenges in efficiently acquiring phase information of a clock signal at a short cycle and adjusting the phase at a longer cycle, leading to signal distortion and increased power consumption.
Innovation Solution
A clock and data recovery circuit comprising a phase detection unit, filtering unit, phase information summing unit, and phase interpolator that generates early and late phase detection signals, up and down signals, and first and second phase control signals to adjust the clock signal phase, allowing for phase information summation over a longer cycle and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If phase information is acquired at a short cycle, then phase adjustment speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the phase adjustment process into two distinct paths: a fast path for coarse phase adjustment and a slow path for fine phase adjustment. The fast path uses a first counter that operates at a shorter cycle to quickly acquire phase information and make initial adjustments. The slow path uses a second counter that operates at a longer cycle to perform fine-tuning. This segmentation allows the system to achieve fast phase locking without continuously operating high-speed components, thereby reducing power consumption while maintaining adjustment speed.
2Measurement precision
If phase detection and adjustment operations are performed frequently, then phase accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of the phase detection and adjustment frequency based on the locking state of the CDR circuit. When the circuit is in an unlocked state, the first counter operates at a higher frequency to quickly acquire phase information and achieve locking. Once locked, the system transitions to the second counter operating at a lower frequency for maintenance. This dynamic frequency adjustment ensures high phase accuracy during acquisition while reducing power consumption during steady-state operation.
Solution Approach 2:
The patent uses periodic action by implementing two different operational cycles: a short cycle for the first counter during acquisition and locking, and a long cycle for the second counter during maintenance. The control logic periodically switches between these two modes based on the locking status, allowing frequent phase detection when needed and infrequent detection when stable, thereby balancing accuracy with power consumption.
3Device complexity
If a simple phase adjustment mechanism is used, then device complexity is reduced, but phase adjustment precision deteriorates
Solution Approach 1:
The patent segments the phase adjustment mechanism into two distinct counters with different functions: a first counter for coarse phase adjustment and a second counter for fine phase adjustment. The first counter handles large phase errors with lower precision requirements, while the second counter handles small phase errors with higher precision requirements. This segmentation allows each counter to be optimized for its specific function, achieving high overall precision without requiring a single complex high-precision counter.
Solution Approach 2:
The patent applies local quality by assigning different precision levels to different parts of the phase adjustment process. The first counter uses a coarser resolution appropriate for initial phase acquisition and large adjustments, while the second counter uses a finer resolution appropriate for precision tuning near the locked state. This localized optimization of precision matches the actual needs of each adjustment stage, achieving high overall precision with minimal circuit complexity.
Data Source
AI summary
A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering unit during a summing-up time; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals.