CDR Frequency Detector Using Edge Logic for Low-Swing Signals
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Solution Overview
Problem
Existing frequency acquisition methods for clock and data recovery circuits, such as phase-frequency detectors and counter-based detectors, are inefficient, particularly with low-swing signals and require complex multi-bit arithmetic operations, making them difficult to implement effectively.
Innovation Solution
A frequency detector circuit utilizing a transition detector, delay circuits, and combinational logic to generate UP and DOWN signals based on edge outputs, allowing for efficient frequency detection without multi-bit arithmetic operations, and enabling conversion to phase detection mode via a selection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counter-based frequency detectors are used, then frequency detection capability is provided, but device complexity and space requirements increase due to multi-bit counters and arithmetic operations
Solution Approach 1:
The frequency detection function is segmented into three independent edge detection circuits, each detecting a specific edge transition. This segmentation allows each circuit to be simple while the combination provides comprehensive frequency detection capability, avoiding the need for complex multi-bit counters.
Solution Approach 2:
The patent replaces the mechanical/arithmetic operation-based frequency detection (multi-bit counters and arithmetic operations) with an edge-triggered digital logic system. This substitution eliminates complex arithmetic operations while maintaining frequency detection accuracy through combinatorial logic analysis of edge transitions.
2Measurement precision
If phase-frequency detectors are used, then frequency detection is enabled, but they are not suitable for digital CDR and require complex implementation
Solution Approach 1:
The patent extracts the essential frequency detection function from complex PFD implementations by focusing only on edge transition detection. By taking out the core functionality and implementing it through simple edge-triggered circuits followed by combinatorial logic, the design achieves PFD-like frequency detection capability with much simpler implementation suitable for digital CDR.
Solution Approach 2:
The patent changes the operational parameters from continuous phase-frequency comparison to discrete edge transition detection. This parameter change simplifies the detection mechanism while maintaining the ability to determine frequency relationships, making it easier to manufacture and implement in digital CDR systems.
3Measurement precision
If rotational frequency detectors are used, then frequency detection is provided, but they do not work well with low-swing signals
Solution Approach 1:
The patent applies preliminary action by using edge-triggered detection circuits that capture transitions at their instant of occurrence. This preliminary capture of edge information before any complex processing ensures that even low-swing signals are accurately detected, as the edge-triggered circuits respond to voltage transitions rather than requiring sustained signal levels.
Solution Approach 2:
The patent creates multiple copies of the edge detection function through three parallel edge detection circuits, each monitoring a specific edge transition. This copying approach ensures that frequency detection reliability is maintained across different signal conditions, including low-swing signals, by providing redundant detection paths that can be logically combined.
Data Source
AI summary
A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.