CDR Circuit Frequency Dispersion Control for SATA Compatibility
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Solution Overview
Problem
The connection between different generations of SATA devices often results in frequency dispersion issues due to operational frequency differences, leading to abnormal operations in receiver apparatuses, as the clock/data recovery (CDR) circuit fails to maintain its own frequency when following the transmitter's frequency.
Innovation Solution
A frequency adjusting method and apparatus that utilize a phase-lock loop (PLL) and CDR circuit in the receiver apparatus, which includes a frequency detector and controller to switch between phase and frequency modes, ensuring the receiver clock follows the transmitter clock only when the frequency difference exceeds a threshold, thereby preventing frequency dispersion by adjusting the operational frequency of the outer apparatus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CDR circuit follows the transmitter frequency to enable communication with higher-generation SATA devices, then compatibility is improved, but frequency stability deteriorates causing the receiver to lock to the transmitter frequency and be unable to return to its own frequency
Solution Approach 1:
The CDR circuit dynamically switches between two operational modes: phase mode for frequency following and frequency mode for maintaining own frequency. This dynamic switching allows the system to adapt to different operational conditions, following the transmitter frequency when needed while maintaining stability when connected to same-generation devices
Solution Approach 2:
The invention changes the operational parameter (frequency following behavior) of the CDR circuit based on detected conditions. When a frequency difference exceeding a threshold is detected, the system switches from phase mode to frequency mode, effectively changing how the receiver handles frequency synchronization
2Measurement precision
If the CDR circuit operates in phase mode to follow the outer data signal frequency, then frequency synchronization is improved, but frequency dispersion occurs when the frequency difference exceeds the threshold
Solution Approach 1:
The frequency detector continuously monitors the frequency difference between the receiver clock and transmitter clock, providing feedback to the controller. When the frequency difference exceeds the threshold, the feedback triggers a mode switch from phase mode to frequency mode, preventing frequency dispersion while maintaining synchronization when appropriate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents frequency dispersion in the CDR circuit, allowing stable data transmission by synchronizing the operational frequencies of different SATA generations, ensuring the receiver apparatus operates within its designated frequency range.
Implementation Method 1
The receiver apparatus includes a phase-lock loop (PLL) and a CDR circuit. The PLL outputs a transmitter clock according to an operational frequency of the receiver apparatus
Implementation Method 2
the CDR circuit generates a receiver clock according to the outer data signal or transmitter clock
Data Source
AI summary
A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus according to its operational frequency and a PLL of the receiver apparatus outputs a transmitter clock according to an operational frequency of the receiver apparatus. The CDR circuit of the receiver apparatus generates a receiver clock according to the outer data signal. The CDR circuit is set in a phase mode such that the receiver clock follows transmitting frequency of the outer data signal. Then, a difference between frequencies of the receiver clock and the transmitter clock is checked. If the difference is larger than a threshold value, an operational frequency of the outer data signal is reduced.