Receiver Initialisation TRIZ Cases
- Bit-Deskewing I/O with Strobe-Tracked Clock Recovery
Separate strobe and data clock recovery keeps sampling aligned, reducing jitter and encoding overhead in high-speed parallel I/O.
- Clock Data Recovery with Multi-Step Tracking for Large Offsets
Multi-step frequency tracking and dynamic accumulator ranges let clock data recovery lock under large offsets while maintaining jitter tolerance.
- Clock Recovery Circuit With Dual-Mode Retiming for Low Jitter
Dual resync and retimer modes adjust delay and clock phase to cut latency, reduce jitter, and avoid extra power-hungry CDR stages.
- Clock Recovery Circuit for All-Slave Ring Frequency Control
A PLL and reference clock keep all-slave ring nodes within frequency limits, preventing rotating unlock and data errors.
- Dual-PLL Clock Recovery for Synchronization During Link Outages
Two PLLs split clock tracking and holdover, letting slave nodes detect timing error and correct resynchronization after downstream outages.
- Configurable SerDes Architecture for Multi-Mode Lock Timing
One SerDes architecture switches between point-to-point and point-to-multipoint modes to balance lock time, jitter, and manufacturing cost.
- Single-Source Clock Recovery With PLL Jitter Cleanup
Recovered data timing is cleaned by a PLL and fed back as the reference clock, cutting jitter and removing external oscillators.