Retimer Equalizer Training During Link Speed Negotiation

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Solution Overview

Problem

Retimers with adaptive equalizers face challenges in supporting communication protocols with different signal constellations and symbol rates, particularly during link speed negotiation, where high baud rates lead to extended link training times and potential performance degradation due to sudden signaling speed changes and spectral deficiencies.

Innovation Solution

The implementation of retimer modules and methods that include an analog-to-digital converter, equalizer, clock recovery module, and adaptation module, which digitize receive signals, derive sampling clocks based on equalization errors, and enable coefficient updates only during stable conditions, ensuring adequate equalization and minimizing performance degradation during link speed negotiation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If retimers perform equalizer training at high baud rates during link speed negotiation, then communication speed is improved, but link training time is extended beyond the module response time

Engineering Contradiction:
Improvecommunication speedVSAvoidlink training time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs equalizer training before link speed negotiation is complete, during the module response time period. By preparing the equalizer coefficients in advance at lower speeds, the system avoids the need for extensive training when transitioning to higher baud rates, thus resolving the contradiction between achieving high communication speed and minimizing link training time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts the equalizer training process based on the current baud rate and link conditions. The equalizer coefficients are updated adaptively during link speed negotiation, allowing the system to optimize performance at each speed transition while maintaining training within the module response time constraints.

Inventive Principle:
Principle #15Dynamics

2Reliability

If retimers update equalizer coefficients continuously during link speed negotiation, then equalization performance is improved, but system stability deteriorates due to sudden signaling speed changes

Engineering Contradiction:
Improveequalization performanceVSAvoidsystem stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent prevents harmful effects by disabling equalizer coefficient updates during periods of unstable link conditions or sudden baud rate changes. This preliminary protective measure avoids the instability that would result from updating coefficients when the signal characteristics are rapidly changing, thus maintaining system stability while preserving equalization performance during stable periods.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent implements a feedback mechanism that monitors link stability and baud rate transitions. Based on this feedback, the system intelligently controls when to enable or disable equalizer updates, ensuring that coefficient updates only occur when link conditions are stable enough to support reliable equalization, thereby balancing performance and stability.

Inventive Principle:
Principle #23Feedback

3Device complexity

If retimers use a fixed sampling clock frequency, then clock recovery simplicity is improved, but adaptability to different baud rates deteriorates

Engineering Contradiction:
Improveclock recovery complexityVSAvoidbaud rate adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent employs a single fixed-frequency sampling clock that serves multiple baud rates through oversampling. This universal clock approach simplifies the clock recovery architecture while maintaining adaptability to different symbol rates, as the fixed clock can accommodate various baud rates by adjusting the sampling relationship rather than requiring separate clocks for each rate.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11424968B1Retimer training during link speed negotiation and link training
Publication Date: 2022.08.23 CREDO TECHNOLOGY GROUP LTD
  • US11424968B1 patent drawing
  • US11424968B1 patent drawing
  • US11424968B1 patent drawing

AI summary

Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.