SerDes Receiver Timing Recovery with Decoupled FFE Adaptation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional signal equalization methods in communication systems suffer from performance and cost limitations, particularly in serializer/deserializer (SerDes) receivers, due to interactions between timing recovery loops and feed-forward equalizers (FFE), leading to suboptimal bit error rates and adaptability issues.

Innovation Solution

A method and device for timing recovery decoupled FFE adaptation in SerDes receivers, utilizing a time-interleaved interface with an interleave specific enable/disable vector to decouple FFE adaptation from the timing recovery loop, enabling phase optimization in mission mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If joint adjustment of timing recovery and equalization is performed, then convergence speed is improved, but convergence accuracy deteriorates due to coupling between the two functions

Engineering Contradiction:
Improveconvergence speedVSAvoidconvergence accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent segments the joint adjustment function into separate independent functions: timing recovery adjustment and equalization adjustment. The timing recovery unit adjusts the sampling phase based on timing error detection, while the equalization unit adjusts equalization coefficients based on signal quality metrics. This segmentation eliminates the coupling effect that caused accuracy deterioration while maintaining convergence speed through coordinated but independent adjustment mechanisms.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If separate adjustment of timing recovery and equalization is performed, then convergence accuracy is improved, but convergence speed deteriorates

Engineering Contradiction:
Improveconvergence accuracyVSAvoidconvergence speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent implements preliminary action by having the timing recovery unit operate first to establish optimal sampling phase alignment before the equalization unit begins its coefficient optimization. This sequential preliminary action ensures that equalization operates on properly aligned signals, improving accuracy while the coordinated timing reduces overall convergence time compared to completely independent adjustments.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If coupled adjustment mechanism is used, then adjustment speed is improved, but adjustment accuracy deteriorates due to interference between functions

Engineering Contradiction:
Improveadjustment speedVSAvoidadjustment accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces an intermediary mechanism where the timing recovery unit and equalization unit communicate through standardized interfaces and control signals. The timing recovery unit provides phase alignment information to the equalization unit, and the equalization unit feeds back signal quality metrics. This intermediary communication structure enables coordinated adjustment speed while preventing direct interference between the adjustment algorithms, thereby maintaining accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4348949B1Method and device for timing recovery decoupled fee adaptation in serdes receivers
Publication Date: 2026.05.13 MARVELL ASIA PTE LTD
  • EP4348949B1 patent drawingFigure 1
  • EP4348949B1 patent drawingFigure 2
  • EP4348949B1 patent drawingFigure 3

AI summary

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.