Phase Detector Calibration for Gain and Offset Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase detectors in high-speed communication systems suffer from gain errors and phase offsets due to varying I/C ratios and unmatched delays, leading to non-optimal phase sampling and performance variations across different silicon wafers.
Innovation Solution
A phase detector apparatus that generates error and reference pulses, combines them into a phase detector pulse, and includes an ADC with full-scale calibration, along with a calibration loop to adjust phase offsets, ensuring consistent gain and reducing phase errors through digital filtering and phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional linear phase detectors use XOR logic gates to generate output currents, then the phase detector can determine optimal phase sampling points, but the I/C ratio varies from silicon wafer to silicon wafer causing gain variations
Solution Approach 1:
The patent changes the parameter being measured from the varying I/C ratio to a time-based measurement. By measuring the time duration of voltage levels at the XOR output and using this to calculate phase difference, the system achieves gain consistency across different wafers while maintaining phase sampling accuracy. The time-based approach eliminates the I/C ratio variation problem.
2Ease of operation
If latches are used to store and pass data in the phase detector, then data can be properly timed, but the inherent latch delay adds offset to the error pulse
Solution Approach 1:
The patent uses feedback by measuring the time duration of voltage levels at the XOR output and using this measurement to calculate the phase difference. The system feeds back the time measurement results to determine phase relationship, which compensates for the latch delay offset and achieves accurate phase measurement despite the inherent delay.
3Measurement precision
If delay is inserted into the data path to compensate for latch delay, then phase offset can be reduced, but it is very difficult to match this delay to the clock-to-Q delay of the latch
Solution Approach 1:
The patent replaces the mechanical delay matching approach with a time-based measurement system. Instead of physically matching delays through circuit design, the system measures the actual time durations of voltage levels and uses these measurements to calculate phase difference. This substitution eliminates the complexity of delay matching while achieving the same offset reduction goal.
Data Source
AI summary
The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.