Physical Layer Transceiver Calibration for Packet Latency Consistency
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Solution Overview
Problem
The variation in packet latency across different clock domains in an Ethernet physical layer transceiver makes it difficult to determine and account for the required timestamp adjustments, especially when either or both PHYs are reset, leading to unpredictable latency variations.
Innovation Solution
Determine transmit and receive latency values separately during initial training, using methods such as resetting clocks simultaneously, aligning synchronization pulses, and storing latency values in a look-up table to account for latency variations until subsequent training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate clock domains operate at different clock rates (312.5 MHz for PCS, 800 MHz for PMA), then data transport between clock domains is enabled, but packet latency varies due to non-multiple clock rates causing irregular edge coincidence
Solution Approach 1:
The patent applies preliminary action by measuring and storing latency values in a lookup table before actual data transmission occurs. During initial link training, the system pre-characterizes the latency behavior across clock domain boundaries by injecting test packets and recording arrival times. These pre-measured latency values are then used to compensate for timing variations during normal operation, eliminating the need for real-time latency calculation and ensuring consistent packet timing despite clock rate differences.
2Measurement precision
If timestamp adjustment is used to account for latency, then packet timing accuracy can be improved, but latency variation makes it difficult to determine the required adjustment value
Solution Approach 1:
The patent uses copying by creating a lookup table that stores pre-measured latency values for different clock phase relationships. Instead of performing complex real-time latency calculations, the system copies the appropriate pre-characterized latency value from the lookup table based on the current clock phase state. This copying approach provides accurate timestamp adjustment values without requiring complex computational logic during data transmission.
3Adaptability or versatility
If PHY reset is performed, then system state can be reinitialized, but latency variation changes making previous calibration invalid
Solution Approach 1:
The patent applies dynamics by making the latency compensation value dynamic rather than static. The lookup table is organized to provide different latency values based on the current clock phase relationship, which changes dynamically after PHY resets. The system continuously monitors clock phase alignment and selects the appropriate pre-measured latency value from the lookup table, allowing the latency compensation to adapt dynamically to changing system states after resets without requiring full re-calibration.
Data Source
AI summary
A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.