Referenceless PLL Frequency Acquisition Using Phase Zone Detection
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Solution Overview
Problem
Existing communication systems require a reference clock to acquire the clock signal embedded in a data stream, which increases cost and design complexity due to the need for a high-cost crystal oscillator and complex clock distribution.
Innovation Solution
A method and integrated circuit that vary control settings of an oscillator across a specified tuning range to lock to the input data stream without a reference clock, using a phase-locked loop and phase zone detection to distinguish true lock from false lock settings based on transitions in the error zone.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock is used to center the PLL output frequency and determine lock status, then the PLL can reliably acquire and maintain the correct frequency, but the system cost and design complexity increase due to requiring a high-cost crystal oscillator and complex clock distribution
Solution Approach 1:
The patent removes the reference clock component from the system entirely. Instead of using a reference clock to center the PLL output and determine lock status, the invention uses a different approach: it varies the oscillator control settings across a tuning range and determines lock status by detecting transitions in the error zone without requiring any external reference signal. This extraction of the reference clock eliminates the associated cost and complexity while maintaining reliable frequency acquisition through the phase zone detection method.
2Measurement precision
If a reference clock is used to determine lock status by comparing to divided recovered clock, then lock detection accuracy is improved, but the system requires additional high-speed clock distribution infrastructure
Solution Approach 1:
The patent makes the system self-sufficient by eliminating the need for an external reference clock. The lock detection is performed using the recovered clock itself and the input data stream, without requiring any external reference signal for comparison. The phase zone detection circuit uses the recovered clock to sample the input data and detect transitions in the error zone, allowing the system to determine lock status using only its own internal signals rather than requiring external reference infrastructure.
3Adaptability or versatility
If the tuning range of the oscillator is increased to cover potential frequency drifts, then the system adaptability improves, but the likelihood of false lock increases
Solution Approach 1:
The patent employs a dynamic, multi-stage approach to oscillator tuning. Instead of using a fixed wide tuning range that could cause false locks, the system dynamically adjusts the tuning range through multiple evaluation stages. In the first stage, a wider tuning range is used to quickly acquire potential lock points. In the second stage, the tuning range is narrowed and the error zone size is increased to verify true lock and eliminate false locks. This dynamic adjustment of parameters allows the system to maintain both wide adaptability and high reliability.
Solution Approach 2:
The patent performs preliminary frequency acquisition in a first evaluation stage using a larger tuning range to identify potential lock points. After finding candidate lock settings, the system then performs a second evaluation stage with a narrower tuning range and larger error zone to verify which candidates are true locks versus false locks. This preliminary action of finding candidates first, then verifying them, allows the system to maintain wide adaptability while preventing false locks through the two-stage verification process.
Data Source
AI summary
An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input data stream are determined at least in part according to a bit error rate. The bit error rate is based on transitions of the input data stream occurring in an error zone, the error zone being a predefined phase zone of a sample clock sampling the input data stream. When two control settings that cause the oscillator to lock or false lock are in a same locking region based on proximity of the control settings to each other, a preferred control setting is determined between the two according to respective values of the two control settings. True lock settings are distinguished from false lock settings based on an evaluation of bit errors that occur in an expanded error zone.