Single-Source Clock Recovery With PLL Jitter Cleanup
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Solution Overview
Problem
Existing clock and data recovery techniques require expensive external clock sources, such as crystal oscillators, and additional integrated circuits for clean-up clock circuits, which is undesirable for reducing jitter in clock signals.
Innovation Solution
A receiver circuit performs clock and data recovery using only a single data input source, incorporating a clean-up phase lock loop to reduce jitter and generate a stable clock, which is then used to produce a reference clock, eliminating the need for external clock sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If expensive crystal oscillators or voltage controlled crystal oscillators are used to generate reference clocks, then clock stability is improved, but circuit cost and complexity increase
Solution Approach 1:
The system uses the recovered clock signal itself to generate the reference clocks needed for operation, rather than requiring external crystal oscillators. The clean-up phase lock loop processes the recovered clock to produce stable reference clocks, making the system self-sufficient and eliminating expensive external components.
Solution Approach 2:
The clean-up phase lock loop acts as an intermediary between the recovered clock signal and the reference clock generation. It filters and stabilizes the recovered clock signal, transforming it into suitable reference clocks for the CDR circuit operation.
2Manufacturing precision
If additional integrated circuits are added for clean-up clock circuits, then jitter reduction is improved, but device complexity increases
Solution Approach 1:
The clean-up phase lock loop functionality is integrated within the existing receiver circuit rather than being implemented as a separate external integrated circuit. This merging approach reduces the total component count while maintaining jitter reduction capabilities.
Solution Approach 2:
The phase lock loop circuit performs multiple functions: it acts as both a clean-up circuit for jitter reduction and as a reference clock generator. This multi-functionality eliminates the need for separate dedicated circuits for each function.
3Measurement precision
If multiple external clock sources are used, then clock recovery accuracy is improved, but cost and ease of manufacture worsen
Solution Approach 1:
The system extracts and utilizes the clock information already present in the incoming data signal, making it self-sufficient without requiring external clock sources. The recovered clock is then processed to provide all necessary reference clocks for accurate data recovery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the need for external clock sources, achieves low jitter in the recovered clock, and allows for efficient clock and data recovery without additional integrated circuits or expensive oscillators, enhancing the stability and cost-effectiveness of the recovery process.
Implementation Method 1
A clean-up phase lock loop circuit reduces jitter in the recovered clock. The cleaned-up clock (the output of the clean-up clock circuit) is subsequently used in applications that require low jitter in the clock signal.
Data Source
AI summary
A receiver circuit reduces the need for external clock sources such as crystal oscillators. The receiver circuit makes use of only a single source, the data input, for performing clock and data recovery. A clock and data recovery circuit receives data and at least one reference clock. The clock and data recovery circuit recovers the clock for the input data using the data input and a reference clock. A clean-up phase lock loop circuit reduces jitter in the recovered clock. The recovered clock from the clock and data recovery circuit is input to the clean-up phase lock loop to produce a clean clock. The clean clock is feed into a clock reference circuit. The clock reference circuit generates the reference clock for the clock and data recovery circuit. As such, the reference clock is based on feed back from the recovered clock. The clock and data recovery circuit obtains a meta-stable state because the loop bandwidth of the clean-up phase lock loop is substantially less than a loop bandwidth for the phase lock loop in the clock reference generator circuit. A clock and data recovery circuit, which does not use a clean-up phase lock loop, is also disclosed. For this configuration, the recovered clock, output from the clock and data recovery circuit, is input directly to the clock reference circuit.