PAM-4 Data Clock Recovery Controller with Envelope Detection
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Solution Overview
Problem
Current data communication technologies face challenges in recovering Pulse-Amplitude Modulation 4 (PAM-4) data and data clock at optimum frequency and phase, especially in high data rate scenarios, leading to Inter Symbol Interference (ISI) and high Bit Error Rate (BER), which complicates the design of compact and cost-effective devices for monitoring applications like automation factories.
Innovation Solution
The implementation of an envelope detector in conjunction with Mueller-Muller detector and other digital signal processing circuits, such as clock and data recovery feed forward equalizer (CDR FFE) and decision feedback equalizer (DFE) data path, to accurately detect the true peak of the received data and generate a recovered data clock with optimal frequency and phase, reducing the need for multiple ADCs and minimizing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high data rate transmission (PAM-4) is used, then data communication speed is improved, but Inter Symbol Interference (ISI) increases leading to high Bit Error Rate (BER)
Solution Approach 1:
The patent applies preliminary action by performing equalization processing before data recovery. The feed-forward equalizer (FFE) and decision feedback equalizer (DFE) are used to pre-compensate for ISI effects on the received signal, thereby reducing BER before the data is finally recovered. This preliminary equalization action addresses the ISI problem caused by high data rate transmission.
2Device complexity
If data clock is not included in transmission to reduce electronic circuits, then device complexity is reduced, but accurate data clock recovery becomes difficult
Solution Approach 1:
The patent applies feedback principle through the decision feedback equalizer (DFE) structure. The DFE uses previously decided data symbols to generate feedback signals that compensate for ISI, improving the accuracy of current symbol detection. This feedback mechanism enables accurate data recovery even without explicit clock information in the transmitted signal.
Solution Approach 2:
The patent applies self-service by using the transmitted data signal itself to generate the clock recovery reference. The receiver extracts clock information from the incoming PAM-4 signal through self-clocking mechanisms, eliminating the need for separate clock transmission while maintaining synchronization accuracy.
3Measurement precision
If multiple ADCs are used to improve data recovery accuracy, then measurement precision is improved, but production cost increases
Solution Approach 1:
The patent merges the functions of multiple ADCs into a single ADC by implementing digital signal processing techniques. The FFE and DFE structures perform equalization in the digital domain, replacing the need for multiple parallel ADC channels. This consolidation reduces the number of ADC components required while maintaining data recovery accuracy through sophisticated digital processing.
Data Source
AI summary
The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.