Clock Delay Circuitry for Non-Source-Synchronous DDR Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-source-synchronous systems face challenges in accurately sampling data signals due to varying loop delays, especially when switching from single data rate (SDR) to double data rate (DDR) modes, without the use of timing windows or synchronous signals, which increases costs by requiring additional communication lines.
Innovation Solution
A method involving a clock-sending device with clock delay circuitry that edge-aligns the internal clock signal with received data signals and delays it by specific phase amounts to generate edge-aligned clock signals for optimal sampling, allowing for DDR communication without relying on timing windows or synchronous signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing windows are used for tuning operations, then sampling accuracy is improved, but device complexity and cost increase due to additional communication lines
Solution Approach 1:
The patent extracts and eliminates the timing window mechanism from the system, achieving accurate sampling without requiring additional synchronous signal lines. The solution uses the existing clock signal and data signal interactions to determine optimal sampling points, removing the need for separate timing control infrastructure.
Solution Approach 2:
The patent introduces a tuning operation that uses data pattern recognition as an intermediary mechanism. Instead of directly using timing windows to control sampling, the system performs tuning by recognizing predetermined data patterns, which indirectly establishes the correct sampling timing without requiring additional communication lines.
2Reliability
If loop delay varies due to temperature or manufacturing differences, then system adaptability is reduced, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent implements dynamic loop delay compensation through tuning operations. Instead of relying on fixed manufacturing precision to control loop delay, the system dynamically adjusts sampling timing by performing tuning operations that adapt to the actual loop delay conditions, which may vary due to temperature or manufacturing differences.
Solution Approach 2:
The patent changes the sampling timing parameter based on recognized data patterns. By monitoring when data patterns are correctly received and recognized, the system adjusts the sampling timing parameter to compensate for loop delay variations, maintaining reliable operation across different manufacturing tolerances and environmental conditions.
3Productivity
If DDR mode is implemented without synchronous signals, then data rate is improved, but measurement precision of sampling points deteriorates
Solution Approach 1:
The patent implements feedback through data pattern recognition to maintain sampling accuracy in DDR mode. The system sends predetermined data patterns and uses the recognition results as feedback to determine whether sampling points are correctly aligned, allowing high-speed DDR operation without synchronous signals while maintaining measurement precision through this closed-loop approach.
Data Source
AI summary
A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.