Clock Recovery Circuit for All-Slave Ring Frequency Control
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Solution Overview
Problem
Communication systems face challenges in maintaining a stable clock frequency across nodes, particularly when there is no dedicated clock master, leading to issues like rotating unlock conditions and frequency fluctuations, which can result in data errors and perceptible gaps.
Innovation Solution
A communication system with a clock recovery circuit that allows all nodes to operate as slaves, using a phase-locked loop (PLL) coupled with a frequency comparator and oscillator to selectively choose between a reference clock and the incoming bitstream frequency, ensuring no node is dedicated as a master, thus preventing inappropriate configuration and frequency drifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a dedicated clock master is assigned to one node, then clock frequency stability is improved, but system adaptability deteriorates because the master node cannot be dynamically changed
Solution Approach 1:
The patent implements dynamic master node selection where any node can become the clock master based on real-time system conditions. The master node is no longer fixed but can be dynamically assigned to different nodes, allowing the system to adapt to changing conditions while maintaining clock stability through the elected master.
Solution Approach 2:
Each node in the network is designed with universal functionality to potentially serve as a clock master. All nodes possess the capability to generate and distribute clock signals, eliminating the need for dedicated master hardware and enabling any node to assume the master role as needed.
2Adaptability or versatility
If all nodes operate as slaves without a dedicated master, then system adaptability is improved, but clock frequency stability deteriorates leading to frequency drift
Solution Approach 1:
The patent implements a feedback mechanism where nodes continuously monitor clock signal quality and frequency stability. Based on this feedback, nodes can elect a new master if the current master's clock drifts beyond acceptable thresholds, ensuring both adaptability and frequency stability are maintained.
Solution Approach 2:
The system performs self-regulation through automatic master election and re-election processes. When frequency drift is detected, the network automatically selects a new master node without external intervention, maintaining clock stability while preserving the all-slave operational mode.
3Ease of operation
If clock recovery circuits recover clock from incoming bitstream without reference to master, then ease of operation is improved, but reliability deteriorates due to rotating unlock conditions
Solution Approach 1:
The patent introduces a reference clock as an intermediary between the incoming bitstream and the local digital subsystem. The reference clock acts as a stable timing reference that mediates the clock recovery process, preventing rotating unlock conditions while maintaining the simplicity of automatic clock recovery.
Solution Approach 2:
The system prepares reference clocks in advance at each node before clock recovery is needed. These pre-prepared reference clocks provide a cushion against potential synchronization failures, ensuring that even if the incoming bitstream clock is unstable, the system has a reliable fallback timing source.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures stable data transfer within an acceptable frequency range, preventing rotating unlock conditions and data errors by automatically triggering a reference clock when frequency deviations occur, allowing all nodes to operate as slaves without a dedicated master, thereby maintaining synchronization and reducing the risk of data errors.
Implementation Method 1
The master clocking signal may be recovered by a phase-locked loop, for example, at each of the various slave nodes 12a-c.
Implementation Method 2
An oscillator can be provided within the communication system that can produce a reference clock independent of an incoming bitstream received by the phase-locked loop.
Data Source
AI summary
A communication system, clock recovery circuit, and method are provided for allowing data to be transmitted across a communication system and between clock recovery circuits absent a clock master specifically designed for one node of the communication system. Absent a clock master, the communication system is permitted to enter into an all slave mode, with periodic unlock conditions possibly rotating about the communication system ring topology. However, the unlock condition can be readily detected and if the received data bitstream formed into a recovered clock exceeds a threshold above or is less than a threshold below a reference clock generated during instances of unlock, then the clock recovery circuit will fix the synchronizing clock to the reference clock, and cause the bitstream to resynchronize to the reference clock before the reference clock is again disabled to allow the communication system to re-enter the all slave and rotating unlock condition. Periodic application of a reference clock interspersed with periodic application of a clock having transitions equal to the incoming bitstream proves advantageous in avoiding a design where a dedicated master must be used within a specified communication system node.