PHY Transceiver Clock-Domain Latency Calibration for Stable Timestamps
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Solution Overview
Problem
The variation in packet latency across different clock domains in Ethernet physical layer transceivers makes it difficult to determine and account for the required timestamp adjustments, especially when either or both PHYs are reset, leading to disruptions in data transport.
Innovation Solution
A method and physical layer transceiver design that separately determines and accounts for transmit and receive latency values during initial training, using synchronization pulses and look-up tables to fix latency contributions across clock domain boundaries, thereby reducing latency variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate clock domains operate at different clock rates (312.5 MHz for PCS, 800 MHz for PMA), then data transport capability is improved, but packet latency variation increases
Solution Approach 1:
The patent measures and stores latency values in advance during link training, creating a lookup table of pre-determined latency characteristics for different clock phase relationships. This preliminary measurement allows the system to compensate for latency variation without real-time calculation, resolving the contradiction by preparing latency correction data before data transport begins.
Solution Approach 2:
The patent changes the parameter of clock phase alignment by adjusting the phase relationship between the 312.5 MHz PCS clock and 800 MHz PMA clock. By controlling when data is sampled across clock domain boundaries and storing latency values corresponding to different phase alignments, the system can select optimal phase relationships that minimize latency variation while maintaining high-speed data transport.
2Measurement precision
If timestamp adjustment is used to account for latency, then latency compensation is improved, but measurement precision deteriorates due to latency variation
Solution Approach 1:
The patent implements feedback by measuring the actual latency experienced by data packets traversing between clock domains and using this measured information to adjust timestamps. The system continuously monitors latency characteristics and updates timestamp adjustments based on measured values from the lookup table, creating a closed-loop system that improves measurement precision despite inherent latency variation.
Solution Approach 2:
The patent performs preliminary latency measurements during link training and stores these values in a lookup table before actual data transport begins. This advance measurement allows the system to have pre-calculated timestamp adjustment values ready, improving the precision of latency compensation without requiring complex real-time calculations that would be affected by latency variation.
3Reliability
If PHY reset is performed to reinitialize the system, then system reliability is improved, but latency variation changes making timestamp adjustment difficult
Solution Approach 1:
The patent performs preliminary latency measurements and stores values in a lookup table during link training, which occurs after PHY initialization but before data transport. When PHY reset occurs, the system can re-perform this preliminary measurement and update the lookup table, ensuring that timestamp adjustments remain accurate despite changes in latency characteristics caused by the reset. This preliminary action before data transport ensures reliability is maintained while latency variation is accounted for.
Data Source
AI summary
A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.