CDR Loss-of-Lock Detection Using Phase Request Accumulation
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Solution Overview
Problem
Existing clock and data recovery (CDR) systems face challenges in accurately detecting loss of lock conditions, particularly in the presence of serial data stream jitter, which affects re-locking efficiency and requires complex circuitry.
Innovation Solution
A loss of lock detector is implemented that generates a binary signal based on phase adjustment requests, using an accumulator to accumulate absolute phase increments and applying filtering and hysteresis to improve detection accuracy, reducing circuit complexity and susceptibility to phase jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rotational detector techniques are used to detect loss of lock by sampling serial data stream for different phases, then loss of lock detection capability is provided, but circuit complexity increases and susceptibility to phase jitter remains
Solution Approach 1:
The patent extracts the essential information for loss of lock detection by monitoring only the phase adjustment requests from the phase control loop, rather than implementing the complex rotational detector that samples data stream for different phases. This extraction approach maintains detection capability while significantly reducing circuit complexity.
Solution Approach 2:
The patent introduces an accumulator as an intermediary element that integrates phase adjustment requests over time. This accumulator serves as a mediator between the phase control loop and the loss of lock detector, converting the complex phase adjustment dynamics into a simplified metric that indicates lock status without requiring complex sampling circuitry.
2Reliability
If rotational detector techniques sample data for different phases to monitor data eye, then loss of lock detection is achieved, but the system becomes more complex and slower to initiate re-locking
Solution Approach 1:
The patent continuously monitors and accumulates phase adjustment requests in real-time, maintaining a ready state that allows immediate detection of loss of lock conditions. This preliminary continuous monitoring eliminates the delay associated with rotational detectors that must complete multiple phase sampling cycles before detecting loss of lock, enabling faster re-locking initiation.
3Productivity
If phase adjustment requests are monitored without filtering and hysteresis, then detection speed is maintained, but detection accuracy deteriorates due to jitter and noise
Solution Approach 1:
The patent implements feedback mechanisms through filtering and hysteresis operations on the accumulated phase adjustment requests. The filter provides feedback that smooths out short-term variations caused by jitter, while hysteresis provides feedback that prevents premature or spurious loss of lock detections. These feedback mechanisms maintain detection speed while significantly improving detection accuracy.
Solution Approach 2:
The patent applies filtering and hysteresis as protective measures beforehand to cushion the detection system against the harmful effects of jitter and noise. This prior cushioning prevents false detections and improves measurement precision without significantly impacting detection speed, as the filtering and hysteresis operations work continuously in the background.
Data Source
AI summary
An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.