CDR Proportional Path Calibration Against Parasitic Capacitance
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Solution Overview
Problem
The gain of the proportional path in existing CDR circuits is reduced due to parasitic capacitance, leading to incorrect data sampling.
Innovation Solution
A CDR circuit with a phase detector, proportional path, and integral path, utilizing a charge pump circuit and variable capacitor to adjust the capacitance of the variable capacitor based on the detection result, thereby maintaining the oscillation signal frequency and improving data sampling accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL-based CDR circuit is used, then the circuit structure is simple, but the gain of the proportional path is reduced due to parasitic capacitance, leading to incorrect data sampling
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect from the proportional path by introducing a separate calibration circuit. This calibration circuit measures and compensates for the parasitic capacitance impact, effectively removing its harmful influence on the proportional path gain while maintaining the original simple PLL structure
Solution Approach 2:
The patent changes the capacitance parameter of the variable capacitor dynamically through calibration. By adjusting the capacitance value based on detected phase error and parasitic capacitance compensation, the proportional path gain is maintained at the desired level, preventing the gain reduction that would otherwise occur due to parasitic capacitance
2Measurement precision
If the proportional path gain is reduced due to parasitic capacitance, then the circuit complexity remains low, but the measurement precision of data sampling deteriorates
Solution Approach 1:
The patent introduces a calibration circuit as an intermediary component that mediates between the phase detector and the variable capacitor. This intermediary measures the phase error, calculates the required capacitance adjustment to compensate for parasitic capacitance, and controls the variable capacitor accordingly, thereby maintaining sampling precision without significantly increasing overall circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the impact of parasitic capacitance on the gain of the proportional path, enhancing the accuracy of data sampling in the CDR circuit.
Implementation Method 1
the variable capacitor generates a proportional control signal based on the voltage control signal
Data Source
AI summary
A clock data recovery (CDR) circuit includes a phase detector circuit, a proportional path, an integral path, and an oscillator circuit. The phase detector circuit is configured to receive input data and detect the input data based on an oscillation signal to output a detection result. The proportional path is configured to output a proportional control signal based on the detection result. The proportional path includes a charge pump circuit and a variable capacitor. The charge pump circuit generates a voltage control signal based on the detection result. The variable capacitor generates the proportional control signal based on the voltage control signal. The integral path is configured to output an integral control signal based on the detection result. The oscillator circuit is coupled to the proportional path and the integral path and configured to generate the oscillation signal based on the proportional control signal and the integral control signal.