CDR Performance Monitoring Circuit With Phase-Shifted Clock BIST
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Solution Overview
Problem
The performance of Clock and Data Recovery (CDR) circuits is degraded due to unacceptable dithering in the digital code, leading to significant jitter in the recovery clock, which affects high-speed data transmission applications.
Innovation Solution
A Built-In Self-Test (BIST) circuit is integrated into a system-on-chip to measure the performance of the CDR circuit by evaluating the phase of the clock using a delay controller and a CDR performance monitoring circuit, which adjusts the phase of the input clock to optimize the CDR circuit's performance based on the magnitude of jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a CDR circuit is used to detect phase and generate recovery clocks, then high-speed data transmission is enabled, but dithering in digital code causes jitter in the recovery clock
Solution Approach 1:
The patent implements a feedback mechanism where the BIST circuit continuously monitors the digital code output from the CDR circuit and detects dithering patterns. Based on this detection, the BIST circuit generates control signals to adjust the phase of the reference clock, creating a closed-loop system that actively compensates for dithering-induced jitter and stabilizes the recovery clock
Solution Approach 2:
The patent changes the phase parameter of the reference clock dynamically based on BIST circuit detection results. By adjusting the phase of the reference clock in response to detected dithering conditions, the system optimizes the CDR circuit operation to minimize jitter in the recovery clock while maintaining high-speed data transmission
2Measurement precision
If a BIST circuit is added to measure CDR performance, then jitter measurement capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the BIST circuit functionality with the existing CDR circuit by integrating the jitter measurement and phase adjustment capabilities into the same circuit block. The BIST circuit shares resources with the CDR circuit, including the phase interpolator and reference clock path, thereby achieving comprehensive jitter measurement and compensation without proportionally increasing overall device complexity
Solution Approach 2:
The BIST circuit is designed with multi-functionality, serving both as a performance measurement tool and as an active compensation mechanism. The same circuit components are used for both detecting dithering patterns and generating control signals for phase adjustment, eliminating the need for separate measurement and correction subsystems
Data Source
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AI summary
A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.