Digital Circuit Testing TRIZ Cases

Using DLL or PLL clock synchronization signals, this case detects SoC voltage glitch attacks with low silicon overhead and no added sensors.

Grouped timing event monitors can be selectively enabled by branch to preserve detection accuracy while cutting unnecessary circuit power use.

An external monitor converts selected clock signals into PWM and compares timing against an independent clock to detect generator faults earlier.

Smaller microsectors and a MicroNOC data path cut FPGA configuration time while improving allocation precision and transaction speed.

Phase-adjustable launch and capture timing measures critical path delay more accurately than ring oscillators, including setup and hold effects.

An LMS-based wander measurement approach estimates transfer function in noisy 1588 timing systems, improving accuracy and shortening test time.

MUX-based compression shares SRAM I/O scan paths to cut transistor count and area while preserving test coverage and reliability.

Delayed time-window sampling and least-squares estimation cut clock frequency error from measurement noise without brute-force circuitry or processor load.

Programmable sine and cosine weighting in a PLL cancels target spurs and enables precise spur magnitude measurement for screening timing circuits.

A configurable ring oscillator separates NBTI and CHC effects in CMOS aging studies while enabling DC, transient, and current characterization.

A sampling and signature-check path verifies high-speed serializer output without a deserializer, saving IC area and power.

Converts high-frequency clock phase differences into a measurable duty cycle, enabling accurate on-chip phase selection with less interference and cost.

Sequentially addressed ring oscillators with shared counting and shift-register readout improve wafer-level variation coverage and data trustworthiness.

A dual-output scan multiplexer boosts digital test coverage beyond 99% while limiting added chip area and power use.

Measures delay differences between aged and reference paths with TDC calibration to avoid frequency-shift overestimation.

Phase-shifted clock testing monitors CDR dithering and tunes input clock delay to measure and reduce recovery clock jitter.

Detecting waveform slope polarity changes lets an SoC disable ADC activity between transitions, cutting bus traffic and power dissipation.

By decoupling power domains and monitoring GPIO logic transitions during ramp-down, this case isolates each SoC POR trip point accurately.

Dual counters and IIR filtering improve clock frequency ratio tracking for precise, low-jitter monitoring in high-speed electronic systems.

Selective multiplexer-based test paths improve semiconductor scan accuracy, cut unnecessary testing, and reduce power, time, and cost.

When remote time references drop out, a trained ML model uses device parameters to control IC clock drift and maintain synchronization.

A modular circuit compares clock frequency with a reference or timestamp to catch radar clock faults and attacks before they disrupt operation.

Merged expected-result and mask signals let an on-chip comparator decode multiple scan chains on fewer pins, cutting chip test time and cost.

Equalizer transistors balance phase detector output voltages before sensing, reducing parasitic load mismatch and improving clock synchronization.

Shared MUX compressors in SRAM I/O DFT circuits reduce transistor count and test area while preserving shift and capture paths.

A short-phase timer and calibrated detectors catch fast clock, glitch, and stop anomalies with low latency and fewer false assertions.

A voltage follower precharges a switchable filter capacitor, then shorts a resistor to cut transients and speed tuning in sensitive signal paths.

Delayed clock and reference edge comparison with latch tuning enables fast, accurate jitter detection without heavy processing.

Integrated bit write and hold functions inside a flip-flop standard cell cut external circuitry, power use, and array area in memory design.

A gated selection circuit with master and slave latches preserves scan input transfer between shared-clock flip-flops for accurate scan testing.

A replica clock adjustment circuit measures PVT-driven delay shifts and aligns clock swing values to keep memory clock and data signals synchronized.

On-substrate bias switching and ADC measurement test power FET resistance without probe needles, avoiding parasitic resistance and particle transfer.

A TDC-based PLL test circuit uses lookup-table parameter changes to verify 312.5-3500 MHz outputs with one test pattern.

Periodic equalizer transistors balance loaded output voltages before sensing, improving phase detection accuracy and synchronization.

Separate master and slave latches with mode-specific clocks cut memory scan chain test power while preserving functional operation.

Direct hardware measurement uses delayed start-up pulses in a competing-path ring oscillator to capture latch setup and hold windows accurately.

By routing VLV test signals through the main output stage, this GPIO screens low-core-Vdd defects without large area or high peak currents.

Diode-connected transistors in a scan flip-flop input multiplexer reduce hold time needs, cutting hold buffers, area, routing, and power.

A dummy transmitter sweeps common-mode voltage in loopback mode to expose LVDS receiver defects across the full input range.

Closed-loop comparison and logic control stabilize internal clock duty cycles in memory, improving high-frequency read/write accuracy.

Clock edge ratios in a cascaded charge pump setup replace direct current measurement, enabling accurate wafer-level efficiency assessment.

By comparing regulator and target supply voltages, this circuit flags latchup and clock loss so ICs can shut down before radiation damage spreads.

Embedded detection elements track signal changes in a programmable gate array to enable real-time function coverage analysis during control unit testing.

Monitors regulator and target supply voltage differences to detect latchup and clock interruptions in radiation-exposed integrated circuits.

A control-guided monitoring circuit observes selected IC nodes even when scan operations fail, improving debug speed and failure analysis.

Timed hardware, fuse, and software overrides let chips bypass unstable logic during bring-up and validate fallback states without re-spins.

Smaller microsectors and a microNOC cut FPGA over-allocation, speed partial reconfiguration, and improve debug trace data handling.

Real-time voltage or power monitoring with staged gain reduction improves oscillation detection accuracy and cuts misclassification risk.

Sequential addressing, multiplexing, and pulse counting let dozens of ring oscillators be measured quickly for trustworthy wafer variation data.

Selective time-measurement sampling with least squares cuts clock estimation error while avoiding brute-force circuit complexity.