Scan Chain Monitoring Circuit for IC Node Debugging
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently debugging and monitoring nodes within a scan chain due to failures in the scan operation, which can hinder complete observation of sequential logic elements.
Innovation Solution
The integrated circuit incorporates a fail analysis circuit with a control unit, monitoring circuit, and multiplexers to perform selective monitoring and debugging of observation nodes, enhancing the efficiency of node analysis and failure detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If scan chain operation is used to observe sequential logic elements, then testability is improved, but debugging efficiency deteriorates when scan operation fails
Solution Approach 1:
The patent introduces a monitoring circuit as an intermediary component that parallel-monitors sequential logic elements independently of the scan chain operation. This mediator allows direct observation of node values without relying on scan-in/scan-out operations, thus maintaining debugging efficiency even when scan chain fails
Solution Approach 2:
The monitoring circuit performs preliminary monitoring of sequential logic elements during normal circuit operation, capturing node values before scan operations are attempted. This preliminary action ensures that node information is already available if scan operation subsequently fails
2Loss of information
If scan cells are reconfigured for scan operation, then observability of internal values is improved, but circuit functionality is temporarily interrupted
Solution Approach 1:
The monitoring circuit enables continuous observation of sequential logic elements throughout circuit operation, including during periods when scan cells are reconfigured for scan operations. This ensures uninterrupted monitoring capability while maintaining the ability to perform scan-based testing when needed
3Reliability
If complete scan chain is implemented to cover all sequential logic, then coverage is improved, but circuit complexity increases
Solution Approach 1:
The monitoring circuit serves multiple functions: it monitors sequential logic elements during normal operation, provides debug information independent of scan chain status, and works alongside the scan chain system. This multi-functionality achieves comprehensive coverage without requiring separate dedicated monitoring infrastructure
Solution Approach 2:
The patent combines the monitoring function with the existing sequential logic elements and circuit operation, rather than adding completely separate monitoring infrastructure. The monitoring circuit integrates with the scan chain control structure, merging multiple functions into a unified system that achieves comprehensive coverage
Data Source
AI summary
An integrated circuit and an electronic device including the integrated circuit are provided. An integrated circuit includes a sequential logic circuit, which includes a first scan cell that is configured to receive a scan input, and a plurality of scan cells sequentially connected in series from the first scan cell, a control unit, which is configured to receive a selection signal including an output of each of the plurality of scan cells, and is further configured to output a control signal responsive to the selection signal, and a monitoring circuit, which is configured to receive the control signal, is configured to perform first monitoring of first data at a first node that is an observation node in the sequential logic circuit responsive to the control signal, and is configured to output a result of the first monitoring to a monitoring node.