Scan Chain Flip-Flop Circuit for Signal-Loss-Free Testing
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Solution Overview
Problem
In scan chain circuits, the loss of scan input signals between flip-flops can lead to errors during scan testing due to the sharing of clock signals, resulting in unreliable test results.
Innovation Solution
The implementation of a flip-flop circuit with a selection circuit, master latch circuit, and slave latch circuit, including specific transistor configurations and inverters, to manage scan input signals and clock signals, ensuring accurate signal transfer and reducing signal loss during scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple flip-flops share a clock signal in a scan chain circuit, then power consumption is reduced and productivity is improved, but signal loss occurs during scan testing leading to decreased reliability
Solution Approach 1:
The patent introduces a scan enable signal as an intermediary control mechanism that mediates between the shared clock signal and the scan input signal transmission. This scan enable signal selectively activates or deactivates the signal path through the flip-flops, preventing signal loss while maintaining the power-efficient shared clock architecture. The scan enable signal acts as a gatekeeper that ensures proper signal propagation only when needed for scan testing.
Solution Approach 2:
The patent implements dynamic control of the scan chain by using the scan enable signal to dynamically activate or deactivate the signal transmission path. This dynamic mechanism allows the circuit to adapt its behavior based on whether scan testing is being performed or normal operation is required, thereby preventing signal loss during scan testing while maintaining efficient power consumption during normal operation.
2Adaptability or versatility
If scan input signals are transmitted through connected flip-flops, then scan testing functionality is achieved, but incorrect signals may be transferred leading to test errors
Solution Approach 1:
The patent implements a feedback mechanism through the scan enable signal that monitors and controls the transmission of scan input signals through the flip-flop chain. This feedback control ensures that signals are only transmitted when properly enabled, preventing incorrect signal propagation and ensuring test result accuracy while maintaining scan testing functionality.
Solution Approach 2:
The scan enable signal serves as an intermediary control element that sits between the scan input signal source and the flip-flop chain. This intermediary mechanism ensures that only valid and properly timed signals are transmitted through the scan chain, preventing incorrect signal transfer while maintaining the adaptability needed for scan testing operations.
3Manufacturing precision
If a selection circuit is added to manage scan input signals, then signal transfer accuracy is improved, but device complexity increases
Solution Approach 1:
The patent designs the selection circuit with multi-functionality, where the scan enable signal and associated circuitry serve multiple purposes: controlling signal transmission during scan testing, maintaining normal operation during regular circuit function, and preventing signal loss. This universal approach improves signal transfer accuracy without proportionally increasing device complexity, as the same structural elements serve multiple functional roles.
Data Source
AI summary
A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.