Memory Scan Chain Latch Architecture for Lower Test Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing scan chain architectures suffer from high power consumption due to the overhead current consumption of D flip flops in both functional and test modes, which is undesirable for efficient testing of memory devices like flip flops or latches.
Innovation Solution
The proposed scan chain architecture incorporates low threshold voltage transistors for the master latch and standard threshold voltage transistors for the slave latch, with separate clocking mechanisms for functional and test modes, utilizing a multiplexer to select between functional and test inputs, thereby reducing power consumption without affecting functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard D flip flop architecture is used for scan chain elements, then testing functionality is achieved, but power consumption increases due to overhead current in both functional and test modes
Solution Approach 1:
The scan chain element is segmented into two separate latches: a master latch for functional mode operation and a slave latch for test mode operation. This segmentation allows each latch to be optimized for its specific function, with the master latch using low threshold voltage transistors for continuous operation and the slave latch using standard threshold voltage transistors activated only during test mode, thereby reducing overall power consumption while maintaining testing functionality.
Solution Approach 2:
The invention dynamically switches between functional and test modes by enabling different latches based on the operating mode. The master latch is continuously active for functional operation, while the slave latch is dynamically enabled only during test mode through mode selection logic. This dynamic operation ensures that the high-power test mode circuitry is active only when needed, reducing average power consumption.
2Productivity
If low threshold voltage transistors are used for continuous operation, then functional mode performance is improved, but current leakage increases during operation
Solution Approach 1:
Different threshold voltage characteristics are applied locally to different parts of the circuit based on their functional requirements. The master latch uses low threshold voltage transistors where continuous operation and fast switching are critical for functional mode performance. The slave latch uses standard threshold voltage transistors where leakage reduction is more important since it operates intermittently only during test mode. This local differentiation optimizes both performance and power efficiency.
Solution Approach 2:
The slave latch operating in test mode uses periodic clocking only when test operations are performed, rather than continuous operation. The mode selection logic enables the slave latch periodically during test mode while keeping it disabled during functional mode, thereby minimizing current leakage from the low threshold voltage transistor path while maintaining functional performance when needed.
Data Source
AI summary
A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.