Power FET Built-In Self-Test for Probe-Free Resistance Measurement
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Solution Overview
Problem
Existing methods for testing power FETs on semiconductor substrates face issues such as the introduction of parasitic resistance and particle transfer using automated test equipment, particularly when testing large areas covered by power FETs, which are significant on the substrate.
Innovation Solution
A built-in self-test circuit is integrated onto the substrate, utilizing a switch controller to alternate the biasing of power FETs, an ADC to digitize voltage drops, and a processor to calculate source-drain resistance, eliminating the need for external probes and avoiding parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automated test equipment with probe needles is used to test power FETs, then testing can be performed externally, but parasitic resistance is introduced and particles are transferred between wafers
Solution Approach 1:
The patent implements a built-in self-test circuit on the substrate that eliminates the need for external probe needles. The test circuit integrates switching devices, current sources, and measurement circuitry directly on the substrate to perform resistance measurements internally, thereby avoiding parasitic resistance and particle transfer associated with external probing methods
Solution Approach 2:
The patent extracts the testing function from external automated test equipment and relocates it onto the substrate itself. By integrating the test circuitry directly with the power FETs, the measurement function is embedded within the device under test, eliminating the harmful interaction between external probes and the device
2Ease of operation
If probe needles are used for testing, then external testing is possible, but the method transfers particles between wafers
Solution Approach 1:
The substrate performs its own testing through integrated circuitry that measures resistance without requiring external contact. The built-in test circuit uses on-substrate switching devices and measurement circuitry to evaluate power FET performance, completely avoiding particle transfer issues associated with physical probe contact
3Measurement precision
If built-in self-test circuit is integrated on substrate, then parasitic resistance is avoided, but device complexity increases
Solution Approach 1:
The patent merges the test circuitry with the power FET structure by integrating switching devices, current sources, and measurement circuitry onto the same substrate. This consolidation achieves accurate resistance measurement while managing complexity through shared substrate real estate and integrated design
Solution Approach 2:
The built-in test circuit is designed to test multiple power FETs on the substrate using shared measurement resources. The circuit can selectively activate different FETs and measure their resistance sequentially, providing universal testing capability that reduces overall system complexity compared to dedicated test circuits for each device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate and reliable testing of power FETs without external probes, reducing parasitic resistance and particle transfer, while efficiently covering large substrate areas.
Implementation Method 1
Measuring the drain-source resistance of the power FETs, when the FET is on, is used for testing the FETs
Data Source
AI summary
A circuit includes first and second power devices that include first and second field effect transistors (FET). A first channel is located between a first drain and a first source of first FET and a second channel is located between a second drain and a second source of second FET. First and second drains are coupled to first common junction and first and second sources are coupled to second common junction. The first common junction is configured to receive a current. A switch controller is coupled to a first gate of the first FET and to a second gate of the second FET to apply a bias voltage to the first and second gates one by one and in turn. An analog to digital converter coupled to first common junction and second common junction and configured to alternately digitize a voltage of the first channel or the second channel.