Scan Compression Pin Encoding for Faster Chip Test Output
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Solution Overview
Problem
As chips become increasingly complex, existing testing methods require longer times to perform tests, leading to higher costs and production delays, especially due to the inefficiencies in scan-in and scan-out processes, where scan-out is typically slower than scan-in and bottlenecks the testing process.
Innovation Solution
Implementing an on-chip comparator with enhanced pin utilization by receiving and processing multiple scan-in chains and a merged expected test-result and masking-instruction signal on fewer pins, allowing for efficient comparison and masking of test results directly on the chip, thereby reducing the need for external output and leveraging the speed advantage of scan-in operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple scan-in chains are processed through external test equipment with traditional scan-out methods, then testing completeness is improved, but test time increases and productivity decreases
Solution Approach 1:
The patent merges the expected test-result signal and masking-instruction signal onto the same scan-in chains that carry test data. This consolidation allows the chip to receive both test patterns and comparison instructions through the same input interfaces, eliminating the need for separate scan-out operations to external equipment for retrieving expected results and masking information.
Solution Approach 2:
The on-chip comparator performs the comparison between actual test results and expected results directly on the chip without requiring external test equipment to retrieve and compare the data. The chip serves its own testing needs by internally comparing results and generating pass/fail outcomes, thereby eliminating the time-consuming external comparison process.
2Measurement precision
If traditional scan-out methods are used to output test results for comparison, then measurement accuracy is maintained, but test speed decreases due to bottleneck
Solution Approach 1:
The patent combines expected test-result signals and masking-instruction signals onto the same physical scan-in chains used for test data input. This merging allows all necessary testing information to be loaded into the chip simultaneously through input pins, eliminating the need for slower scan-out operations to external equipment.
Solution Approach 2:
The on-chip comparator autonomously performs the comparison function internally, retrieving expected results and masking instructions from the same scan-in chains that carry test data. This self-service approach eliminates the external comparison bottleneck while maintaining accurate measurement through direct on-chip comparison logic.
3Reliability
If separate pins are used for expected test-result and masking-instruction signals, then signal integrity is improved, but pin count increases and device complexity increases
Solution Approach 1:
The patent merges expected test-result signals and masking-instruction signals onto the same scan-in chains and input pins. By consolidating these signals onto existing test data pathways, the invention eliminates the need for additional dedicated pins, thereby reducing device complexity and pin count while maintaining proper signal delivery through the shared scan-in infrastructure.
Data Source
AI summary
A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.