Flexible Test Circuit Paths for Accurate Semiconductor Scan Testing
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Solution Overview
Problem
As semiconductor integration increases, existing scan test technologies face challenges such as decreased accuracy of test results and increased costs, necessitating improved testing efficiency and accuracy.
Innovation Solution
A flexible test circuit and integrated circuit design incorporating input and output multiplexers, a test block, and gating circuits to enable flexible test paths and reduce unnecessary testing, thereby enhancing test accuracy and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan test technology is used on highly integrated semiconductor devices, then testing coverage is improved, but test accuracy decreases and testing costs increase
Solution Approach 1:
The test circuit is divided into multiple independent test channels (first test channel, second test channel, etc.), each capable of independently testing different signal paths. This segmentation allows parallel testing of multiple paths simultaneously, improving testing efficiency while maintaining accuracy by dedicating specific resources to each test path.
Solution Approach 2:
The test circuit implements a universal testing architecture that can test both normal signal paths and reversed signal paths using the same hardware infrastructure. The multiplexers and gating circuits enable the system to adaptively configure test paths, allowing a single test channel to perform multiple testing functions, thereby reducing overall testing costs while maintaining comprehensive coverage.
2Reliability
If comprehensive testing of all signal paths is performed, then test coverage is improved, but testing time and costs increase
Solution Approach 1:
The test circuit employs dynamic path selection through control signals that can reversibly switch between normal signal paths and reversed signal paths. This dynamic configuration allows the testing system to adaptively select which paths to test based on test requirements, enabling comprehensive coverage of critical paths while reducing unnecessary testing of non-critical paths, thereby reducing testing time.
Solution Approach 2:
The reversible signal path design allows continuous testing operations by enabling the test circuit to switch between different test modes (normal path testing, reversed path testing) without requiring physical reconfiguration or downtime. This continuity ensures comprehensive test coverage is achieved through efficient sequential or parallel testing of multiple paths.
3Measurement precision
If traditional test structures are used, then implementation simplicity is maintained, but test flexibility and accuracy decrease
Solution Approach 1:
The test circuit introduces intermediary components (multiplexers, gating circuits, control logic) that mediate between the simple existing semiconductor device structure and the required complex testing functionality. These intermediaries enable flexible test path configuration and reversible signal routing without requiring fundamental changes to the device under test, thereby improving test accuracy while managing complexity through modular additions.
Solution Approach 2:
The invention adds a temporal dimension to signal path testing by implementing reversible signal paths that can switch between normal forward-direction testing and reversed backward-direction testing. This dimensional approach to path configuration allows the same physical infrastructure to support multiple test modes, improving test accuracy through comprehensive path verification while avoiding the need for entirely separate test structures.
Data Source
AI summary
A test circuit includes a first input multiplexer configured to receive a first input data signal and a second input data signal, a second input multiplexer configured to receive a first output signal and a third input data signal of the first input multiplexer, a third input multiplexer configured to receive a second output signal and a fourth input data signal of the second input multiplexer, a test block configured to generate an output data signal by performing a test operation based on an output of the third input multiplexer, and a gating circuit configured to receive the output data signal and output the received output data signal to at least one channel.