Very Low Voltage GPIO Screening Through Shared Output Stage
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Solution Overview
Problem
Conventional defect screening methods for low voltage integrated circuit devices face challenges in identifying defects at very low core supply voltages without requiring large circuit areas or high peak currents, limiting their effectiveness in detecting manufacturing defects.
Innovation Solution
A very low voltage (VLV) input/output (I/O) circuit and method that includes a general-purpose GPIO circuit capable of operating in both functional and low core-Vdd optimized test modes, featuring a VLV transmitter and receiver connected to a main output stage to avoid overvoltage violations, enabling defect screening at voltages close to the threshold voltage of Core FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard level shifters are used for defect screening at low voltage, then the test voltage is too high for proper defect screening, but modifying the level shifter design to operate at low voltage leads to high area and high peak currents
Solution Approach 1:
The patent segments the I/O circuit into separate functional blocks: a level shifter block and a defect screening block. The level shifter operates at high voltage to interface with external devices, while the defect screening circuit operates independently at low voltage to test core logic. This segmentation allows each block to be optimized for its specific voltage domain without compromising the other, resolving the contradiction between measurement precision and circuit area.
Solution Approach 2:
The patent introduces an intermediary voltage domain and intermediate buffering circuits between the high voltage I/O interface and the low voltage core logic. This intermediary structure enables proper defect screening at low voltage levels while maintaining compatibility with high voltage external interfaces, avoiding both the too-high test voltage problem and the high area penalty of direct low voltage operation.
2Measurement precision
If level shifters are designed to operate at very low voltage close to threshold voltage, then defect screening at low voltage is enabled, but peak currents become excessively high
Solution Approach 1:
The patent implements dynamic voltage scaling and mode switching in the I/O circuit. During normal operation, the circuit operates at standard voltage levels. During defect screening, it dynamically switches to a low voltage test mode with appropriately scaled test patterns. This dynamic operation enables defect screening at low voltage while avoiding sustained high peak currents that would occur with static low voltage design.
Solution Approach 2:
The patent employs periodic defect screening tests rather than continuous low voltage operation. The defect screening is performed as periodic test sequences during manufacturing or burn-in testing, allowing the circuit to return to normal higher voltage operation between tests. This periodic action enables defect detection while minimizing overall power consumption and peak current exposure.
Data Source
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AI summary
A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.