Chip Speed Detection Circuit for Critical Path Timing Accuracy
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Solution Overview
Problem
Current chip speed detection methods using ring oscillators fail to accurately represent the speed of the critical path due to discrepancies between the oscillator-determined chip speed and actual signal delay on the critical path, particularly due to timing differences between simple gates in the oscillator and complex combinational gates.
Innovation Solution
A speed detection circuit comprising a test signal generator, launch flip-flop, device under test, capture flip-flop, comparator, and control circuit, which uses phase-adjustable clock signals to accurately determine the chip's speed by comparing output signals against a specific pattern, adjusting phases and path lengths to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ring oscillators are used to detect chip speed, then the detection method is simple, but the detected speed does not accurately represent the actual speed on the critical path
Solution Approach 1:
The patent introduces a dedicated test circuit as an intermediary between the ring oscillator and the critical path. This test circuit includes a test signal generator that creates test signals, a launch flip-flop that samples these signals, and a capture flip-flop that captures the signals after they pass through the critical path. This intermediary structure allows accurate measurement of the critical path delay without requiring modification of the actual critical path logic, thus maintaining simplicity while improving accuracy.
Solution Approach 2:
The patent creates a copy of the critical path's timing characteristics through the test circuit. Instead of directly measuring the complex critical path, the test circuit replicates its timing behavior using simpler components (flip-flops and delay elements) that can be accurately measured. The test circuit acts as a simplified model or copy that preserves the essential timing properties of the original critical path.
2Ease of operation
If ring oscillators with simple gates are used, then the oscillator operation is straightforward, but the timing information does not reflect the delay of complicated combinational gates in the critical path
Solution Approach 1:
The patent changes the measurement parameters from oscillation frequency (which reflects average delay) to direct time delay measurement (which reflects actual signal propagation time). The test circuit measures the time difference between launching a test signal and capturing it after it passes through the critical path, providing direct timing information that accurately reflects the delay of complex combinational gates rather than an averaged oscillation period.
3Device complexity
If timing information of flip-flop is not considered, then the detection circuit is simpler, but the chip speed determination is inaccurate
Solution Approach 1:
The patent applies preliminary action by using the launch flip-flop to sample the test signal at a precisely controlled time point before the signal enters the critical path. This preliminary sampling establishes a known reference time that accounts for the flip-flop's own timing characteristics. By capturing the signal after it passes through the critical path and comparing the timing, the circuit accurately measures only the critical path delay while compensating for flip-flop timing effects.
Data Source
AI summary
The present invention provides a speed detection circuit positioned in a chip, wherein the speed detection circuit includes a test signal generator, a launch flip-flop, a device under test (DUT), a capture flip-flop, a comparator and a control circuit. The test signal generator is configured to generate a test signal with a specific pattern. The launch flip-flop is configured to use a first clock signal to sample the test signal to generate a sampled test signal. The device under test is configured to receive the sampled test signal to generate a delayed test signal. The capture flip-flop is configured to use a second clock signal to sample the delayed test signal to generate an output signal. The comparator is configured to determine whether the output signal conforms to the specific pattern to generate a comparison result, for the control circuit to determine a speed of the chip.