Phase-to-Duty-Cycle Clock Test Circuit for On-Chip Phase Selection
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Solution Overview
Problem
Existing phase selection test systems require high frequency clock signals to be driven off-chip for measurement, which causes interference and increases manufacturing costs, and the narrow bandwidths of on-chip components make accurate phase selection challenging.
Innovation Solution
A phase-shift to duty-cycle converter and low pass filter system that converts phase differences into a measurable duty cycle, allowing on-chip measurement without requiring extra-wide bandwidths and external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high frequency clock signals are driven off-chip for measurement, then measurement capability is improved, but interference increases and manufacturing costs increase
Solution Approach 1:
The patent introduces a phase-to-duty-cycle converter as an intermediary device that transforms the high frequency phase difference signal into a low frequency duty cycle signal. This converter acts as a mediator between the high frequency clock signals and the low bandwidth ADC, enabling accurate phase measurement without directly transmitting high frequency signals off-chip, thus avoiding interference and cost increases.
Solution Approach 2:
The patent replaces the traditional mechanical/electrical approach of directly measuring high frequency clock signals with an electronic signal transformation approach. By converting the phase difference into a duty cycle variation at low frequency, the system substitutes direct high frequency measurement with indirect low frequency measurement, eliminating the need for high bandwidth external components.
2Measurement precision
If high frequency clock signals are driven off-chip for measurement, then measurement capability is improved, but manufacturing costs increase
Solution Approach 1:
The phase-to-duty-cycle converter serves as an intermediary that enables the use of standard, low-cost on-chip ADCs with narrow bandwidths to measure high frequency clock phase differences. This intermediary transformation allows the system to avoid expensive high bandwidth external ADCs and measurement equipment, significantly reducing manufacturing costs while maintaining measurement capability.
Solution Approach 2:
The patent changes the frequency parameter of the signal being measured by converting high frequency phase information into low frequency duty cycle information. This parameter transformation allows the use of inexpensive low bandwidth ADCs instead of expensive high bandwidth components, thereby reducing manufacturing costs while preserving the essential measurement function.
3Ease of manufacture
If on-chip components with narrow bandwidths are used, then manufacturing cost is reduced, but accurate phase selection becomes challenging
Solution Approach 1:
The patent substitutes direct high frequency phase measurement with indirect low frequency duty cycle measurement. By transforming the measurement domain from high frequency phase to low frequency duty cycle, the system enables accurate phase selection using narrow bandwidth on-chip ADCs, thus achieving both cost reduction and measurement accuracy.
Solution Approach 2:
The patent applies parameter transformation by converting the phase difference parameter (at high frequency) into a duty cycle parameter (at low frequency). This parameter change allows narrow bandwidth components to accurately represent phase information, resolving the contradiction between using low-cost on-chip components and achieving accurate phase selection.
Data Source
AI summary
A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.