Multi-Power Domain POR Testing via GPIO Trip-Point Detection
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Solution Overview
Problem
Testing power-on-reset (POR) trip points in multi-power domain devices is challenging due to the need for separate PORs in each domain, especially in systems with dual power flow modes, where conventional methods fail to distinguish between different power domains.
Innovation Solution
A method and system for testing multiple PORs in a system-on-chip (SoC) with a multi-power domain architecture under dual power flow mode, involving decoupling power domains and monitoring GPIO pads during supply ramp-down to detect logic transitions at specific thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single-POR testing methods are used in multi-power domain devices, then testing simplicity is maintained, but the ability to distinguish and test individual power domain POR trip points is lost
Solution Approach 1:
The patent segments the power domain testing by decoupling switches that isolate each power domain (first, second, and third power domains) from others. This allows individual POR trip point testing for each domain by controlling the decoupling state of switches, enabling precise measurement of each domain's POR threshold without interference from other domains.
Solution Approach 2:
The patent introduces GPIO pads as intermediary monitoring points that detect logic transitions corresponding to POR trip points. These GPIO pads serve as mediators between the power domain POR circuits and the testing system, enabling external observation and measurement of internal POR events without direct access to the POR trip point nodes.
2Measurement precision
If power domains are decoupled for individual testing, then POR trip point distinction is achieved, but testing time increases due to sequential testing requirements
Solution Approach 1:
The patent employs dynamic switch control where decoupling switches can be rapidly transitioned between coupled and decoupled states. This dynamic switching allows the testing system to sequentially isolate and test each power domain's POR trip point by controlling the switch states, achieving precise domain identification while minimizing the time penalty through efficient sequential testing.
3Reliability
If multiple PORs are implemented in each power domain, then reliable reset functionality is ensured, but testing difficulty increases due to inability to distinguish individual POR behavior
Solution Approach 1:
The patent segments the monitoring function by providing separate GPIO pads for each power domain (first GPIO pad for first power domain, second GPIO pad for second power domain, third GPIO pad for third power domain). Each GPIO pad monitors the POR status of its corresponding power domain independently, enabling the testing system to detect and measure individual POR trip points even when multiple PORs are implemented within each domain, thus maintaining both reliability and testability.
Data Source
AI summary
According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.