Programmable Gate Array Coverage Monitoring via Embedded Detection
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Solution Overview
Problem
Existing methods for testing and analyzing the execution of functions in programmable gate arrays, such as FPGAs, are inefficient and lack real-time coverage analysis capabilities, particularly in emulating control units for vehicles.
Innovation Solution
A programmable gate array equipped with detection elements that determine the execution of function parts by monitoring signal changes, allowing for real-time coverage analysis and evaluation of function performance, facilitated by a computer arrangement that includes a processor unit for result value generation and a test device for simulating control units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional testing methods are used for programmable gate arrays, then the testing process is simple to implement, but real-time coverage analysis capabilities are lacking and testing efficiency is low
Solution Approach 1:
The patent embeds detection elements within the functional units of the gate array, creating a nested structure where monitoring capabilities are integrated inside the computing resources. This allows real-time coverage analysis without adding external monitoring hardware, thus improving testing efficiency while maintaining a compact architecture.
Solution Approach 2:
The patent introduces detection elements as intermediary components that mediate between the functional units and the configuration system. These detection elements monitor signal changes and provide coverage information, enabling real-time analysis without disrupting the normal operation of the gate array.
2Measurement precision
If detection elements are added to monitor function execution, then real-time coverage analysis is enabled, but the device complexity increases
Solution Approach 1:
The patent implements detection elements selectively at specific functional units where coverage monitoring is needed, rather than uniformly across the entire gate array. This localized approach enables precise coverage analysis at critical points while minimizing the overall increase in device complexity.
Solution Approach 2:
The detection elements are designed to serve multiple purposes: they monitor signal changes for coverage analysis, track function execution status, and provide feedback for configuration optimization. This multi-functionality reduces the need for separate dedicated monitoring components, thereby limiting the increase in device complexity.
3Ease of manufacture
If automated placement of detection elements is implemented, then configuration data generation is optimized, but the processing complexity increases
Solution Approach 1:
The patent performs automated placement of detection elements during the configuration data generation phase, before the gate array is physically manufactured or programmed. This preliminary action optimizes the detector positioning algorithm to consider future signal flow patterns, enabling ease of manufacture without requiring complex real-time processing during operation.
Solution Approach 2:
The patent uses a virtual model or copy of the gate array architecture to simulate and optimize detection element placement before implementing it in the actual device. This copying approach allows complex processing algorithms to be developed and tested in silico, simplifying the actual manufacturing process while maintaining high measurement precision.
Data Source
AI summary
A programmable gate array that is set up to perform a function and to use at least one signal by at least one function part of the function when performing the function. The gate array has at least one detection element which is set up to determine, using a change to the signal, whether the at least one function part is run on the gate array when the function is performed, and to provide at least one detection value dependent on the determination. A computer arrangement is also provided, which has such a gate array, a use of such a computer arrangement, a test device which has such a computer arrangement, and a method for generating configuration data for programming such a gate array.