Differential Clock Calibration Circuit for Memory Duty Cycle Control
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Solution Overview
Problem
Semiconductor memory systems face challenges in maintaining accurate duty cycle calibration of internal clock signals, which can lead to deviations and affect reading and writing performance, especially as operating frequencies increase.
Innovation Solution
A calibration circuit comprising a differential input circuit, a comparison unit, and a logical unit that receives and compares oscillation signals to ensure the duty cycle of internal signals reaches a preset range, thereby stabilizing and calibrating the duty cycle to improve test accuracy and reduce deviations caused by the differential input circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of semiconductor memory is increased to meet faster electronic system demands, then the speed and data capacity improve, but the duty cycle deviation of internal clock signals increases, affecting reading and writing performance
Solution Approach 1:
The patent applies preliminary action by performing duty cycle calibration before the semiconductor memory operates at high frequencies. The calibration circuit pre-adjusts the internal clock signals to ensure accurate duty cycles are established before high-speed operations begin, preventing duty cycle deviations that would otherwise occur during high-frequency operation.
Solution Approach 2:
The patent implements feedback through a calibration circuit that continuously monitors and adjusts the duty cycle of internal clock signals. The circuit compares the actual duty cycle against a target value and dynamically adjusts the clock signal parameters to maintain accuracy, creating a closed-loop control system that compensates for frequency-related deviations.
2Device complexity
If conventional differential input circuits are used without calibration, then the device complexity remains low, but duty cycle deviations occur that affect test accuracy and performance
Solution Approach 1:
The patent introduces an intermediary calibration circuit between the differential input circuit and the rest of the memory system. This calibration circuit acts as a mediator that corrects duty cycle deviations without requiring fundamental changes to the existing differential input structure, thereby maintaining simplicity while improving accuracy.
Solution Approach 2:
The patent applies parameter changes by adjusting the duty cycle parameter of internal clock signals through the calibration circuit. The circuit modifies timing parameters and signal characteristics to achieve accurate duty cycles, allowing the system to maintain low complexity while achieving high measurement precision through parameter optimization.
Data Source
AI summary
A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.