Scan Multiplexer Circuit for High-Coverage Digital Testing
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Solution Overview
Problem
Existing test circuits for digital circuits have limited test coverage, typically achieving less than 70-80%, and require additional multiplexers that increase chip area and power consumption to reach higher coverage, falling short of the desired 99% target.
Innovation Solution
A multiplexer with an additional output configured to receive the signal state from the first input when the test mode is activated and set to zero when deactivated, combined with a scanning flip-flop to observe the signal state, reduces transistor count and chip area while increasing test coverage to over 99%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional multiplexers are added to increase test coverage, then test coverage is improved, but chip area and power consumption increase
Solution Approach 1:
The patent combines the functionality of multiple multiplexers into a single multiplexer by adding a second output. This allows one multiplexer to perform the work of what would traditionally require two separate multiplexers, thereby increasing test coverage without proportionally increasing chip area. The single multiplexer routes signals to both the first output (for normal operation) and the second output (for test observation), merging multiple functions into one component.
Solution Approach 2:
The multiplexer is designed with multi-functionality by providing two outputs from a single device. The first output handles normal signal routing while the second output enables test mode observation. This universal design allows the same component to serve both operational and testing purposes, eliminating the need for dedicated test-only multiplexers and reducing overall chip area.
2Reliability
If additional multiplexers are added to increase test coverage, then test coverage is improved, but power consumption increases
Solution Approach 1:
By merging the functions of multiple multiplexers into a single multiplexer with two outputs, the patent reduces the total number of active components. Fewer multiplexers mean fewer transistors switching and fewer logic operations required, directly reducing dynamic power consumption while maintaining enhanced test coverage capabilities.
Solution Approach 2:
The multi-functional multiplexer reduces power consumption by eliminating redundant circuitry. Instead of powering separate multiplexers for normal operation and test modes, a single multiplexer handles both functions, reducing the overall power budget required for signal routing operations during testing.
3Reliability
If traditional test circuits are used, then chip area is minimized, but test coverage remains limited below 99%
Solution Approach 1:
The patent merges test observation functionality into the primary signal routing path by adding a second output to the existing multiplexer. This integration approach avoids creating separate complex test circuits while achieving comprehensive test coverage. The same multiplexer structure serves both operational and testing functions, reducing overall device complexity.
Data Source
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AI summary
The present description relates to an electronic test circuit (200) of a digital circuit (104, 110), comprising a multiplexer (310) having: a first input (A) intended to receive a signal from the digital circuit to be tested; a second input (Te) configured to receive a test mode activation signal (Scan_mode); a third input (Ti); a first output (Z) intended to receive a state of the third input (Ti) when the second input (Te) is activated and a state of the first input (A) when the second input (Te) is deactivated; a second output (NSZ) intended to receive a state of the signal present on the first input (A) or to be set to zero when the second input (Te) is respectively activated or deactivated.