SRAM I/O DFT Circuit Using Shared MUX Compression for Smaller Area
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Solution Overview
Problem
The existing SRAM circuit designs face challenges in scaling down the area of cell arrays and I/O circuits due to limitations in processing, leading to unsatisfactory performance in manufacturability, reliability, power, and area efficiency, particularly with the increasing complexity of technology nodes.
Innovation Solution
The redesign of SRAM circuits incorporates a multiplexer (MUX)-based compression in the I/O DFT circuit, allowing for fewer transistors and shared MUX compressors among multiple I/O pins, which reduces the total area requirement by up to 44% compared to XOR-based compression methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If XOR-based compression is used in I/O DFT circuit, then testing capability is provided, but area consumption is high
Solution Approach 1:
The patent merges multiple scan chains into a single compressed scan chain using MUX-based compression. Multiple input scan chains are combined through multiplexer logic that selectively routes inputs based on control signals, reducing the number of separate test paths while maintaining comprehensive testing capability. This merging approach directly reduces area consumption by eliminating redundant circuitry.
Solution Approach 2:
The MUX-based compression circuit serves multiple functions: it compresses scan chains for area reduction, enables selective testing of different circuit paths through control signals, and maintains compatibility with both normal operation mode and test mode. This multi-functionality allows a single circuit structure to replace what would otherwise require separate dedicated circuits for each function.
2Reliability
If more transistors are used in I/O DFT circuit, then testing coverage is improved, but area efficiency deteriorates
Solution Approach 1:
The patent segments the testing function into multiple independent scan chains that can be individually controlled and compressed. Each scan chain can be selectively enabled or disabled through control signals, allowing comprehensive testing coverage while using fewer total transistors by only activating the necessary segments for each specific test scenario.
Solution Approach 2:
The MUX-based compression circuit dynamically reconfigures the test paths based on control signals. The multiplexers can switch between different input sources and compression ratios depending on the testing requirements, allowing the circuit to adapt its structure rather than requiring a fixed large-scale design that covers all possible test scenarios simultaneously.
3Adaptability or versatility
If separate MUX compressors are used for each I/O pin, then testing flexibility is improved, but device complexity increases
Solution Approach 1:
A single MUX-based compression circuit is designed to handle multiple I/O pins through shared control logic and multiplexer stages. The same compression circuit can be dynamically configured to compress scan chains from different I/O pins by changing control signals, eliminating the need for separate dedicated compressors for each pin while maintaining full testing flexibility.
Solution Approach 2:
The patent merges the compression functionality for multiple I/O pins into a unified MUX-based compression structure. Multiple scan chains from different I/O pins are routed through shared multiplexer resources that selectively route and compress the appropriate inputs based on control signals, reducing overall device complexity while preserving the ability to independently test each I/O pin.
Data Source
AI summary
A circuit includes a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.