Low-Area Scan Flip-Flop Architecture With Reduced Hold Time
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Solution Overview
Problem
The high hold time requirement in scan flip-flops imposes design constraints, leading to increased circuit area, routing complexity, and power usage, particularly in scan chains where multiple flip-flops are connected with multiple hold buffers to meet hold constraints.
Innovation Solution
The introduction of an input multiplexer with diode-connected transistors reduces the effective voltage across other transistors, slowing down their switching speed and thereby reducing the hold time requirement of the scan flip-flop in scan mode, allowing for a decrease in the number of hold buffers needed in scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple hold buffers are added to scan chains to meet hold constraints, then the hold time requirement is satisfied, but the circuit area increases
Solution Approach 1:
The patent changes the voltage parameter by introducing diode-connected transistors that reduce the effective voltage across the multiplexer transistors. This voltage reduction slows down the switching speed, thereby reducing the hold time requirement and eliminating the need for multiple hold buffers in scan chains.
2Reliability
If multiple hold buffers are added to scan chains to meet hold constraints, then the hold time requirement is satisfied, but the routing complexity increases
Solution Approach 1:
By changing the voltage parameter through diode-connected transistors, the patent reduces the hold time requirement, which directly reduces the number of hold buffers needed in scan chains, thereby simplifying the routing complexity.
3Reliability
If multiple hold buffers are added to scan chains to meet hold constraints, then the hold time requirement is satisfied, but the power usage increases
Solution Approach 1:
The patent changes the voltage parameter to reduce hold time requirement, which reduces the number of hold buffers needed. Since each buffer consumes power, reducing their number directly reduces the overall power usage of the scan chain.
4Reliability
If the effective voltage across transistors is reduced to slow down switching speed, then the hold time requirement is reduced, but the setup time may be affected
Solution Approach 1:
The patent applies local quality by introducing diode-connected transistors specifically at the input multiplexer stage where voltage reduction is needed to reduce hold time. This localized voltage reduction affects only the critical path for hold time without significantly impacting the setup time other stages.
Solution Approach 2:
The patent changes the voltage parameter locally at the multiplexer input stage, reducing the effective voltage across specific transistors to slow down their switching speed. This selective parameter change reduces hold time requirement while minimizing impact on setup time.
Data Source
AI summary
In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.