SRAM I/O DFT Circuit With MUX Compression for Smaller Scan Paths
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Solution Overview
Problem
Existing SRAM circuits face challenges in scaling down the area of I/O circuits due to limitations in processing, leading to unsatisfactory performance in manufacturability, reliability, power efficiency, and density, particularly with increasing technology nodes.
Innovation Solution
Redesigning SRAM circuits to incorporate a MUX-based compression in the I/O DFT circuit, allowing for shared scan paths and reducing the number of transistors, and enabling a common MUX compressor for multiple I/O pins, thereby reducing the overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If XOR-based compressors are used in I/O DFT circuits, then test functionality is maintained, but circuit area is larger and transistor count is higher
Solution Approach 1:
The patent merges multiple scan paths into a single shared scan path using MUX-based compression. Multiple input signals from different I/O pins are combined through multiplexers that selectively route signals based on control signals, reducing the total number of transistors and circuit area while maintaining test functionality. This is achieved by combining scan enable signals and data inputs through MUX structures that allow multiple paths to share common resources.
Solution Approach 2:
The MUX compressor structure provides multi-functionality by serving as both a test compression mechanism and a signal routing device. The same MUX structure used for compressing scan paths also functions as a signal router during normal operation, eliminating the need for separate dedicated compression logic and reducing overall circuit area while improving manufacturability.
2Adaptability or versatility
If separate scan paths are used for each I/O pin, then test coverage is comprehensive, but device complexity and area increase
Solution Approach 1:
The patent combines multiple separate scan paths into a unified compressed scan path structure. Multiple I/O pin inputs are merged through MUX stages that selectively activate different input paths based on test requirements, maintaining comprehensive test coverage while reducing structural complexity. The merged structure allows single-path testing of multiple pins through controlled signal routing.
Solution Approach 2:
The scan path structure becomes dynamic through the use of control signals that enable selective activation of different MUX paths. The circuit can dynamically reconfigure which I/O pin connects to which scan path based on test requirements, providing adaptability for comprehensive testing while maintaining a compact static structure that reduces overall device complexity.
Data Source
AI summary
A circuit includes a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.