PLL Test Circuit Using TDC for Single-Pattern Frequency Verification
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Solution Overview
Problem
Existing phase locked loop (PLL) systems require multiple test patterns to verify device under test (DUT) functions at different output frequencies, which is time-consuming and inefficient.
Innovation Solution
A circuit architecture that includes a digital converter, evaluation circuit, and duty correction circuit to adjust the first frequency and duty cycle of input signals, allowing the PLL to generate output frequencies within a wide range using a single test pattern by indexing a lookup table to determine parameter levels, thereby eliminating the need for multiple test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test patterns are used to verify DUT functions at different output frequencies, then verification completeness is improved, but testing time increases
Solution Approach 1:
A single test pattern is designed to universally verify DUT functions across multiple output frequencies. The test pattern includes a time-to-digital converter that can measure different frequency ranges (e.g., 312.5 MHz to 3500 MHz) by adjusting parameter levels, eliminating the need for multiple separate test patterns while maintaining verification completeness.
Solution Approach 2:
The test pattern utilizes parameter level adjustments (e.g., dividing by different integers like 2, 4, 8, 16) to change the effective measurement range of the time-to-digital converter. By changing these parameters, the same test pattern can verify DUT functionality across a wide frequency spectrum without requiring multiple distinct test patterns.
2Loss of time
If a single test pattern is used to cover wide frequency range, then testing time is reduced, but measurement precision may deteriorate
Solution Approach 1:
The frequency measurement range is segmented into multiple sub-ranges, each handled by a specific parameter level setting. The time-to-digital converter uses different division ratios (parameter levels) to accurately measure different frequency segments, ensuring precision is maintained across the entire wide range from 312.5 MHz to 3500 MHz.
Solution Approach 2:
The test pattern dynamically adjusts parameter levels based on the output frequency being tested. The system automatically selects appropriate parameter settings (e.g., different division factors) to optimize measurement precision for each frequency range, allowing a single test pattern to maintain high precision across varying frequencies.
Data Source
AI summary
A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.