Priority Override Circuit for Reversible Silicon Debug States
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Solution Overview
Problem
Conventional semiconductor debugging methods face challenges with unpredictable silicon behavior, leading to expensive device recalls, re-spins, and delays due to irreversible hard configurations that cannot be tested or validated without full tape-outs, and lack flexibility in applying overrides during specific design states.
Innovation Solution
A multilayered, self-correcting override system with hardware, software, and fixed metal programmable states that allows reversible overrides, enabling independent enablement or disablement of critical logic, and includes intelligent priority override controllers to handle unpredictable silicon behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard configurations (hardware metal plug) are used for fallback logic, then device reliability is improved, but device flexibility and reversibility deteriorate
Solution Approach 1:
The patent implements a dynamic configuration system where hard configurations can be selectively enabled or disabled through control logic. The system transitions from static metal plugs to dynamically controllable override circuits that can change state based on operational conditions, allowing the same hardware to provide both reliable fallback functionality and flexible adaptability.
Solution Approach 2:
The override system is segmented into multiple independent override circuits, each controlling specific logic blocks. This segmentation allows selective application of hard configurations only where needed, rather than blanket overrides, enabling partial reversibility and targeted reliability enhancement without compromising overall device flexibility.
2Reliability
If multiple hard configurations are implemented, then device reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs universal override circuit blocks that can be reused across multiple locations in the device. Each override circuit serves multiple functions: providing hard configuration, enabling soft configuration, and allowing dynamic switching. This multi-functionality reduces the need for separate dedicated circuits for each configuration type, thereby managing complexity while maintaining reliability.
Solution Approach 2:
The system changes the state parameters of override circuits through control signals rather than requiring physical reconfiguration. By using enable/disable parameters and selection signals, the system can activate or deactivate multiple hard configurations programmatically, reducing the perceived complexity compared to physically managing multiple metal plugs.
3Manufacturing precision
If validation is performed with particular hardware configuration for one tape-out at a time, then manufacturing precision is maintained, but development time and productivity decrease
Solution Approach 1:
The patent enables preliminary validation of multiple hardware configuration combinations before final tape-out. By incorporating override circuits that allow post-silicon configuration changes, the system permits validation activities to be performed earlier in the development cycle with configurable overrides, rather than requiring complete validation only after each tape-out, thereby accelerating development while maintaining validation rigor.
Solution Approach 2:
The override circuits create virtual copies of configuration states that can be tested without committing to permanent hardware changes. Software or debugger can load different configuration sets into the override circuits, effectively copying and testing multiple hardware configurations in software-controlled environments before finalizing the manufacturing configuration.
4Reliability
If blanket override schemes with hard configuration are used, then device reliability is improved, but time to ship functional samples increases
Solution Approach 1:
The override circuits serve as intermediaries between the hardwired metal plug configurations and the actual logic blocks. This intermediary layer allows soft configuration and debugger control to modify the effective configuration without changing the underlying hard configurations, enabling faster iteration and earlier shipping of functional samples while maintaining the reliability benefits of hard configurations where needed.
Data Source
AI summary
An override circuit for a semiconductor chip including an override interface, a timer, and a priority override controller. The override interface is configured to select between an original value and a selected override value for providing an output value. The timer provides a timeout signal after a predetermined time period after start-up. The priority override controller has a default configuration for controlling the override interface to select the original value as the output value at start-up until the timeout signal is provided, and then to control the override interface to select a fixed metal hardware override value as the selected override value. The priority override controller is configurable to control the override interface to instead select at least one configurable override value as the selected override value upon start-up. The configurable override value may be a software value for diagnostic purposes, or a hardware fuse value as a final value.