CDR PLL Clock Recovery with Fast Lock and Low Power
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Solution Overview
Problem
Existing receiving devices with clock data recovery (CDR) and phase locked loop (PLL) circuits face challenges in reducing power consumption and shortening lock-up time, especially in systems with variable bit rates, where traditional methods to reduce lock-up time are not applicable.
Innovation Solution
The receiving device incorporates a first PLL circuit to extract a clock from received data and a second PLL circuit to multiply the received clock by N, with a control circuit applying a control signal to the first PLL's VCO during packet reception, and uses a control voltage applying circuit to apply an appropriate control voltage to the CDR's VCO, allowing the CDR to operate independently and reducing power consumption by stopping operations during non-reception periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CDR and PLL operate continuously to maintain synchronization, then the lock-up time is reduced, but the power consumption increases
Solution Approach 1:
The control voltage applying circuit pre-charges the capacitor in the loop filter to a voltage corresponding to the expected oscillation frequency before the CDR receives data. This preliminary action allows the VCO to start oscillating at the correct frequency immediately upon receiving data, significantly reducing lock-up time without requiring continuous operation and high power consumption during idle periods
Solution Approach 2:
The system dynamically switches between different operational states: during idle periods, the CDR stops operating to save power while the control voltage is pre-applied; during data reception, the CDR activates immediately with the pre-charged capacitor providing the correct initial frequency. This dynamic state switching resolves the contradiction between continuous operation (short lock-up time) and periodic operation (low power consumption)
2Use of energy by moving object
If the CDR operates independently without continuous PLL support, then power consumption is reduced, but lock-up time may increase
Solution Approach 1:
The control voltage applying circuit performs preliminary charging of the loop filter capacitor before data reception begins. This pre-charging establishes the correct initial voltage level that corresponds to the desired oscillation frequency, enabling the independently operating CDR to achieve synchronization quickly without relying on continuous PLL support, thus maintaining both low power consumption and short lock-up time
Data Source
AI summary
According to one embodiment, a receiving device includes a first PLL circuit, a second PLL circuit, and a control circuit. The first PLL circuit includes a first VCO and extracts a first clock from a received first packet. The second PLL circuit includes a second VCO and outputs a second clock acquired by multiplying the received clock by N. The control circuit applies a control signal of the second VCO to a first line controlling the first VCO during a first time from start of reception of the first packet.