User-Defined Cell Group Partitioning for Circuit Floorplan Synthesis

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Solution Overview

Problem

Microelectronic circuit design faces challenges in physical design and verification due to the complexity of integrating millions of transistors and increasing circuit functionality, particularly in satisfying user-defined criteria for cell groups in floorplans.

Innovation Solution

A method and system that involve obtaining a register-transfer level (RTL) file, generating a gate-level netlist, and partitioning cell groups based on user-defined criteria to create a floorplan, ensuring that cells are optimally placed and synthesized according to specific timing and placement characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If automatic placement tools are used to place cells in a floorplan, then placement speed is improved, but the ability to satisfy user-defined placement criteria deteriorates

Engineering Contradiction:
Improveplacement speedVSAvoidplacement criterion satisfaction
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the floorplan into multiple regions and divides cells into different groups, allowing automatic placement tools to operate on smaller, manageable segments while user-defined criteria are applied specifically to critical regions. This enables parallel processing of non-critical areas (maintaining speed) while focusing manual optimization on important areas (satisfying criteria).

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different placement strategies to different regions of the floorplan based on user-defined criteria. Critical regions with specific timing or placement requirements receive manual optimization attention, while non-critical regions use automatic placement tools. This local differentiation allows the system to maintain high overall productivity while ensuring critical areas meet precise criteria.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If manual optimization is performed to satisfy user-defined criteria, then placement precision is improved, but design time increases

Engineering Contradiction:
Improvecriterion satisfactionVSAvoiddesign time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent divides the design into multiple iterations where only specific cell groups are manually optimized in each iteration rather than the entire floorplan. This segmentation of the optimization process reduces the time investment required for manual work while still achieving criterion satisfaction for critical regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies manual optimization partially - only to specific cell groups that fail to meet user-defined criteria, rather than optimizing the entire floorplan manually. This partial action approach minimizes design time while still achieving the necessary precision for critical areas.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If the floorplan is divided into multiple regions, then placement flexibility is improved, but system complexity increases

Engineering Contradiction:
Improveplacement flexibilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent uses segmentation to divide the floorplan into multiple regions and cell groups, which improves placement flexibility by allowing different optimization strategies for different areas. The system manages this complexity through automated grouping algorithms that organize cells based on their characteristics and criteria satisfaction status.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements automated cell grouping mechanisms that self-organize cells into appropriate groups based on their properties and the user-defined criteria. This self-service approach reduces the burden on the designer to manually manage the complexity of multiple regions, as the system automatically handles the organization and iteration process.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10325050B2User-defined partitions for logical and physical circuit syntheses
Publication Date: 2019.06.18 ORACLE INT CORP
  • US10325050B2 patent drawing
  • US10325050B2 patent drawing
  • US10325050B2 patent drawing

AI summary

A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.