CAD Circuit Design TRIZ Cases
- Boundary Logic Interface Layout for Flexible IC Signal Routing
Moving boundary logic interfaces outside the programmable logic region improves routing flexibility and global network access without using logic fabric resources.
- DAC Current Source Array Layout for Non-Random Error Suppression
Segmented symmetric DAC current source arrays use thermometer, binary, bias, and dummy cells to suppress gradient errors and improve linearity.
- Programmable Logic Fabric Regularity for Fast Design Core Relocation
Identical heterogeneous logic blocks let verified placement, routing, and timing data be reused to relocate or copy PLD design cores faster.
- CLB Internal Routing Architecture With Embedded Bnodes for Local FPGA Paths
Embedded bnodes and centered clock spines improve CLB local routing, cut general routing use, and reduce clock skew in FPGA fabrics.
- AC-Coupled DDR Receiver With Autozeroing for Low VT Drift
An AC-coupled differential receiver with autozeroing cuts VT drift and bit errors while sustaining high DDR bandwidth at low power.
- Signal Processing Accelerator Routing for Lower FPGA Area
A reconfigurable signal processing accelerator network cuts FPGA area, power, and unused blocks by routing data flexibly and enabling processing only after enough input arrives.
- Timing Insulation Circuitry for Stable Partial Reconfiguration
Timing insulation circuitry isolates platform timing changes from user kernels, preserving compatibility during partial reconfiguration updates.
- Hierarchical Partial Reconfiguration for Nested FPGA Regions
Nested partial reconfiguration regions cut bitstream overhead and keep FPGA kernels running during fine-grained reconfiguration.
- FPGA Circuit Configuration Learning for Soft Error Reduction
Machine learning links FPGA operating states and soft error patterns to optimize circuit placement and improve reliability under neutron-induced faults.
- Programmable DDS Output Driver for Low-Distortion Capacitive Loads
Programmable PMOS/NMOS DAC and variable output buffers cut quiescent power while preserving rail-to-rail sinusoidal drive for capacitive loads.
- Multi-Die FPGA Clock Synchronization for Skew and Latency Alignment
Phase detectors and programmable delays align clocks across dies and sectors, reducing skew and latency for easier timing closure.
- Circuit Stencils for Reusing Layout-Dependent Effects in IC Design
Reuse extracted layout-dependent effects through circuit stencils to improve pre-layout IC simulation accuracy and cut design iterations.
- Virtual FPGA Fabric Compilation From OpenCL Kernels
Precompiled virtual fabrics let OpenCL kernels map to programmable logic faster, cutting FPGA configuration time without HDL expertise.
- Multi-FPGA Assertion Checkers for Fast SoC Debug Halt
User-defined assertion checkers halt SoC clocks only on failures, speeding multi-FPGA debug without periodic state-dump slowdowns.
- Operation-Block Array Chaining for FPGA Interconnect Efficiency
Chained operation blocks with ALUs cut FPGA interconnect overhead, improving embedded-system performance, power efficiency, and development speed.
- FPGA Logic Tile Power Gating Without Data Loss
Programmable tile power control lets an FPGA shut down selected logic tiles while preserving output states to cut energy use without data loss.
- Tapped Inductor VCO Topology for High-Q Low-Noise RF Design
A nested tapped inductor topology raises LC tank energy storage to lower noise and current while maintaining high Q at higher RF frequencies.
- Reconfigurable Inter-Block FIFO Sizing for CPU-FPGA Throughput
A common reconfiguration region adjusts inter-block FIFO size on demand, cutting reconfiguration overhead while sustaining CPU-FPGA throughput.
- Circuit Stencil Instantiation for Reusable IC Segment Layouts
Abstracted circuit stencils compress connectivity and constraints so IC segments can be reused across layouts without extra hierarchy or scripting.
- Virtual Fabric Configuration for Faster High-Level FPGA Compilation
Precompiled virtual fabrics cut high-level FPGA compilation time, enabling faster reconfiguration without losing design flexibility.
- Circuit Loop Bit-Assignment Optimization Using Wire Replication
Replicating loop bit-assignment chains into wires and selecting them with a multiplexer cuts EDA runtime and circuit complexity.
- Multi-FPGA Assertion Checkers for Fast SoC Prototype Debug
User-defined assertion checkers stop the prototype clock on failures, enabling faster SoC debug without costly periodic state dumps.
- Signal Processing Accelerator Architecture for Lower FPGA Area Waste
A hybrid signal processing accelerator uses shared interconnect and data-threshold enabling to cut FPGA area waste, cost, and power.