Circuit Stencils for Reusing Layout-Dependent Effects in IC Design
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Solution Overview
Problem
The design flow for integrated circuits faces inefficiencies due to the iterative process of extracting layout-dependent effects (LDE) information, which leads to multiple design iterations, especially at smaller geometry processes, where LDE impacts are significant, and existing methods do not effectively reuse this information for improved circuit design.
Innovation Solution
The reuse of extracted LDE information is facilitated through the use of circuit stencils, where LDE information for circuit segments is extracted from layouts, instantiated in a schematic, and used for simulations without generating a layout, allowing for more accurate simulations and reduced design iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If LDE information is extracted from layout and back-annotated to schematic for re-simulation, then design accuracy is improved, but design iteration time increases
Solution Approach 1:
The patent extracts LDE information from the layout and back-annotates it to the schematic design before final simulation, allowing designers to account for layout-dependent effects earlier in the design process. This preliminary action reduces the need for repeated design iterations by addressing LDE impacts before the layout is finalized, thereby improving design accuracy while reducing overall iteration time.
Solution Approach 2:
The patent implements a feedback mechanism where LDE information extracted from the layout is fed back into the schematic design through back-annotation. This feedback loop allows the simulation results to reflect actual layout effects, enabling designers to make informed adjustments to the schematic based on real layout-dependent behavior, thus improving accuracy without requiring excessive iterations.
2Reliability
If LDE extraction and re-simulation are performed multiple times, then design performance is improved, but productivity decreases
Solution Approach 1:
The patent performs LDE extraction and back-annotation as a preliminary step before final design validation, rather than repeatedly during multiple design iterations. By establishing the LDE information early and using it throughout the design process, the patent improves design performance while avoiding the productivity loss associated with repeated extraction and re-simulation cycles.
3Manufacturing precision
If LDE information is extracted at smaller geometry processes, then manufacturing precision is improved, but design complexity increases
Solution Approach 1:
The patent extracts LDE information early in the design flow before layout optimization, allowing the design team to account for manufacturing precision requirements at smaller geometries from the outset. This preliminary extraction simplifies the overall design process by establishing a baseline for manufacturing accuracy, reducing the complexity that would otherwise arise from repeated adjustments at later stages.
Data Source
AI summary
A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. The circuit stencil includes layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit. Simulation is performed on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment. A layout of at least a portion of the second integrated circuit corresponding to the circuit segment is generated responsive to performing the simulation.