FPGA Circuit Configuration Learning for Soft Error Reduction
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Solution Overview
Problem
Field programmable gate array (FPGA) devices experience soft errors due to neutron beam collisions, leading to malfunctions, and existing countermeasures are inefficient as they do not accurately identify high-risk regions within the device.
Innovation Solution
A circuit configuration optimization apparatus that uses machine learning to collect and analyze data on soft error occurrence frequencies and device operating states, optimizing circuit configurations to reduce malfunctions by learning the correlation between error states and circuit configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If circuits are arranged in high boron concentration regions to increase device functionality, then the device can perform more functions, but the occurrence frequency of soft errors increases significantly
Solution Approach 1:
The patent applies local quality by creating distinct regions within the FPGA device with different boron concentration levels. High boron concentration regions provide enhanced radiation hardness and lower soft error rates, while low boron concentration regions allow for higher density circuit arrangements. The system dynamically assigns circuits to appropriate regions based on their error tolerance requirements and performance needs, thereby resolving the contradiction between functionality and reliability.
Solution Approach 2:
The FPGA device is segmented into multiple regions with different boron concentration characteristics. This segmentation allows independent optimization of each region - some regions prioritize radiation hardness while others prioritize circuit density. The control unit manages this segmentation by allocating circuits to specific regions based on their operational requirements, enabling the device to achieve both high functionality and improved reliability simultaneously.
2Reliability
If noise-robust circuits with error correcting function or redundancy are arranged in high boron concentration regions, then soft error resistance is improved, but device area and complexity increase
Solution Approach 1:
The patent implements local quality by assigning different circuit types to different boron concentration regions. Standard circuits are placed in low boron concentration regions for area efficiency, while only critical circuits requiring high reliability are placed in high boron concentration regions. This selective placement strategy provides soft error resistance where needed without unnecessarily increasing device complexity or area throughout the entire device.
Solution Approach 2:
Instead of applying error correction and redundancy uniformly across the entire device, the patent applies these measures partially - only in high boron concentration regions where circuits are most vulnerable to soft errors. This partial action approach provides adequate protection against soft errors while avoiding the excessive complexity and area overhead that would result from universal error correction implementation.
3Reliability
If circuits are not arranged in high boron concentration regions to avoid soft errors, then soft error occurrence is reduced, but the usable device area decreases
Solution Approach 1:
The patent segments the device area into high and low boron concentration regions, each serving different functional purposes. The high boron concentration regions, while smaller in area, provide critical reliability for error-sensitive circuits. The low boron concentration regions provide larger area for standard circuits. This segmentation allows the device to maximize usable area while maintaining high reliability through strategic placement of circuits in appropriate regions.
Solution Approach 2:
By creating local quality differences through varying boron concentration in different regions, the patent enables circuits to be placed throughout the entire device area rather than restricting placement to only low boron regions. Critical circuits receive enhanced protection through placement in high boron concentration zones, while non-critical circuits utilize the larger area of low boron regions, thereby maximizing overall usable device area while maintaining reliability.
Data Source
AI summary
A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.