Programmable Logic Fabric Regularity for Fast Design Core Relocation
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Solution Overview
Problem
Relocating or reusing large and complex design cores in programmable logic devices is time-consuming due to the need to re-run software design tools for simulation, placement, and routing, which increases design time significantly.
Innovation Solution
Implementing a programmable logic device with multiple heterogeneous logic blocks of identical configuration, allowing configuration data reuse across these blocks through a platform management controller and bitstream generation, enabling efficient relocation and reuse of designs without re-executing design tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional software design tools are re-run to relocate a design core to a different location or different PLD, then the design core can be relocated, but design time increases significantly
Solution Approach 1:
The patent applies copying by creating identical replicas of logic blocks across multiple PLDs. Once a design core is implemented and verified in one logic block, the same configuration can be copied to identical logic blocks in other PLDs without re-running the full software design toolchain, significantly reducing design time while maintaining consistency
Solution Approach 2:
The patent implements universality by designing logic blocks with identical configurations that can serve multiple purposes across different PLDs. The same logic block type can implement the same design core in multiple locations, enabling flexible relocation and reuse without requiring custom design processes for each instance
2Adaptability or versatility
If software design tools are re-executed to relocate large and complex design cores, then the design core can be moved, but the process becomes time-consuming
Solution Approach 1:
The patent applies preliminary action by pre-configuring identical logic blocks with the same structure and capabilities before design core relocation is needed. The logic blocks are prepared in advance to be exact replicas, so when relocation is required, the design core can be moved without re-executing the time-consuming placement and routing processes
Solution Approach 2:
The patent uses copying to replicate the entire logic block configuration including all internal structures and connections. This allows design cores to be moved between identical blocks without re-simulation or re-verification, maintaining productivity while enabling flexible relocation
Data Source
AI summary
A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.