Multi-FPGA Assertion Checkers for Fast SoC Prototype Debug
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SoC prototyping methods using FPGAs often sacrifice debug infrastructure for performance, leading to slow debugging processes and increased computational costs due to periodic state dumps, which complicate the identification and correction of errors.
Innovation Solution
Incorporating user-defined assertion checkers into FPGA prototyping systems that stop the clock upon assertion events, allowing control to be passed to a runtime system for error handling, thereby enabling quick diagnostics and minimal performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic state dumps are implemented for debugging, then debug information is captured, but performance slows down and computational cost increases
Solution Approach 1:
The patent extracts the debugging function from the periodic state dump mechanism and implements it through assertion checkers that operate independently. Assertion checkers monitor specific conditions without requiring full state dumps, thus capturing essential debug information while avoiding the performance overhead of comprehensive periodic sampling.
Solution Approach 2:
Assertion checkers serve as intermediaries between the prototyping system and debug infrastructure. Instead of directly implementing full state dumps, the checkers provide targeted condition monitoring that mediates between performance requirements and debug needs, enabling selective information capture with minimal impact on system performance.
2Reliability
If multiple assertion checkers are supported, then debug coverage is improved, but system complexity increases
Solution Approach 1:
The patent merges multiple assertion checkers into a unified management framework within the prototyping system. The runtime system consolidates checker registration, configuration, and control, allowing multiple checkers to be managed through a single interface rather than requiring separate management for each checker, thus reducing overall system complexity.
Solution Approach 2:
The assertion checker implementation provides universal functionality that handles multiple checkers through a common architecture. The runtime system offers multi-functional capabilities including checker registration, enabling/disabling, and coordinated control, allowing the same infrastructure to manage any number of checkers without requiring checker-specific management code.
3Measurement precision
If clock stopping is implemented on assertion, then diagnostic accuracy is improved, but prototyping time increases
Solution Approach 1:
The patent applies clock stopping locally and selectively rather than globally and continuously. When an assertion checker detects a condition violation, the clock is stopped only for that specific checker and only long enough to capture the relevant state information. This localized approach maintains high diagnostic accuracy while minimizing the time penalty compared to continuous or global clock stopping.
Data Source
AI summary
A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.