Multi-FPGA Assertion Checkers for Fast SoC Debug Halt
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Solution Overview
Problem
Current FPGA-based prototyping systems for SoC designs lack robust debug infrastructure, leading to slow debugging processes and significant performance slowdowns when periodic state dumps occur, complicating the identification and correction of errors.
Innovation Solution
Incorporating user-defined assertion checkers into the FPGA prototyping system that stop the SoC clocks upon assertion events, allowing control to be passed to a runtime system for error handling, thereby enabling quick diagnostics and minimal impact on performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic state dumps are performed in FPGA-based prototyping systems, then debugging information is captured, but performance slowdowns occur
Solution Approach 1:
The patent extracts the state dump functionality from the main system clock domain by using assertion checkers that operate independently and trigger external debugging actions only when assertion violations occur. This separates the debugging mechanism from the performance-critical execution path, eliminating periodic performance slowdowns while maintaining debugging capability.
Solution Approach 2:
The assertion checker acts as an intermediary between the system under test and the debugging infrastructure. Instead of directly implementing periodic state dumps that slow down the system, the assertion checker monitors for specific error conditions and triggers debugging actions only when needed, mediating between continuous monitoring requirements and performance constraints.
2Reliability
If multiple assertion checkers are implemented in a multi-FPGA system, then debugging coverage is improved, but system complexity increases
Solution Approach 1:
The patent implements a universal assertion checker architecture that can be instantiated multiple times across different FPGA devices. Each assertion checker uses the same standardized interface and behavior, allowing multiple checkers to be deployed for comprehensive debugging coverage without proportionally increasing system complexity. The uniform design enables easy replication and management.
Solution Approach 2:
The debugging functionality is segmented into independent assertion checker modules that can be distributed across multiple FPGA devices. Each assertion checker is a self-contained unit that monitors specific assertion conditions, allowing the overall debugging system to scale across multiple devices while maintaining modular complexity management.
3Loss of time
If assertion checkers stop system clocks upon assertion events, then error identification is accelerated, but system operation is interrupted
Solution Approach 1:
The assertion checkers perform preliminary monitoring of assertion conditions continuously in the background without affecting system operation. Only when an assertion violation is detected do they trigger the clock stop action, preventing the need for continuous system interruption while still enabling rapid error identification when issues occur.
Data Source
AI summary
A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.