FPGA Logic Tile Power Gating Without Data Loss
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Solution Overview
Problem
Existing FPGA technologies lack efficient power management capabilities, as they do not allow for programmable power states of logic tiles, leading to inefficient power consumption and potential data loss during partial or complete power-down states.
Innovation Solution
The integration of programmable power-on/power-off circuitry within or external to the logic tiles, enabling individual or group control of power states, allowing for partial or complete power-down of logic tiles during normal operation while maintaining data integrity through output power-down circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If logic tiles are powered down to reduce energy consumption, then power efficiency is improved, but data loss occurs
Solution Approach 1:
The patent applies preliminary action by capturing and storing output data states before the logic tile is powered down. The output capture circuitry saves the data state to a buffer or memory location in advance, ensuring that data is preserved before the power transition occurs, thus preventing data loss while enabling power-down operation
Solution Approach 2:
The patent uses an intermediary mechanism in the form of output capture circuitry and buffer memory that mediates between the logic tile and the external interface. This intermediary captures the data state and maintains it during power-down, allowing the logic tile to be powered off without causing data loss at the interface
2Adaptability or versatility
If programmable power control circuitry is added to logic tiles, then power management capability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the power control functionality into discrete, modular components within each logic tile. Each logic tile contains its own power-down control circuitry and output capture circuitry as separate functional blocks, allowing independent control of power states for different tiles without affecting others, thus managing complexity through modular segmentation
Solution Approach 2:
The patent implements universality by designing the power control circuitry to perform multiple functions: normal logic operation, power-down control, and output data capture. The same circuit infrastructure supports both active and powered-down states, reducing the need for entirely separate circuits and thereby limiting the increase in device complexity
3Loss of energy
If individual logic tiles are powered down selectively, then energy efficiency is improved, but control complexity increases
Solution Approach 1:
The patent applies self-service by enabling each logic tile to autonomously respond to power-down control signals. Each tile contains its own power-down control circuitry that can independently capture and preserve its output state without requiring complex centralized control, thus reducing overall control complexity while enabling selective power management
Data Source
AI summary
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.