Circuit Stencil Instantiation for Reusable IC Segment Layouts
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Solution Overview
Problem
Current integrated circuit (IC) design flows lack full automation and effective reuse of circuit segments, relying on static or hardcoded IP reuse that limits application to specific target locations, requiring significant programming or scripting skills and introducing additional hierarchy when reusing circuit components.
Innovation Solution
The implementation of 'assistive' automation through the creation and instantiation of self-checking circuit stencils, which abstract and compact connectivity information, allowing for the reuse of circuit segments without additional hierarchy, by generating reduced connectivity information and constraints for components, enabling efficient re-use across different IC designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static or hardcoded IP reuse is used, then circuit segments can be reused, but the application is limited to only target locations that match the design source exactly
Solution Approach 1:
The patent transforms static, hardcoded IP reuse into a parameterized system where circuit segments are defined with abstracted connectivity information and parameters. This allows the same circuit segment to be instantiated with different parameter values (such as component counts, dimensions, or electrical characteristics) to adapt to various target locations and design requirements, thereby resolving the contradiction between reusability and adaptability.
2Adaptability or versatility
If Module Generators are used for alternate re-use approaches, then circuit segments can be reused with more flexibility, but significant programming or scripting skills are required
Solution Approach 1:
The patent employs a stencil-based copying mechanism where circuit segments are captured as stencils containing their connectivity information and parameters. These stencils can be copied and instantiated multiple times with different parameter values through simple operations rather than requiring programming or scripting. This approach maintains flexibility while significantly reducing the skill barrier, resolving the contradiction between adaptability and ease of operation.
3Productivity
If traditional IP reuse methods are used, then circuit segments can be reused, but additional hierarchy is introduced
Solution Approach 1:
The patent segments circuit designs into reusable circuit segments with abstracted connectivity information, allowing these segments to be instantiated without introducing additional hierarchy. The stencil mechanism enables direct instantiation of segmented circuit portions while maintaining flat or reduced hierarchical structures, thereby improving productivity while minimizing complexity overhead.
Data Source
AI summary
Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.