DAC Current Source Array Layout for Non-Random Error Suppression
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Solution Overview
Problem
Current DACs face non-random errors due to variations in oxide film thickness, doping, stress, temperature, and power supply voltage, which affect their linearity and resolution, especially in high-resolution applications, where existing common centroid array layouts are insufficient in error suppression.
Innovation Solution
A method for arranging a current source array in a DAC, involving determining the number of rows and columns to create symmetric sub-arrays with thermometer and binary encoding current sources, bias current sources, and dummy cells, arranged to reduce first-order and second-order non-random errors, with thermometer encoding for higher bits and binary encoding for lower bits, and bias current sources generating a bias voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current source cells are arranged in a common centroid array symmetrically in upper, lower, left and right directions, then non-random errors are suppressed, but the error suppression ability is still insufficient for high performance applications
Solution Approach 1:
The patent divides the current source array into multiple sub-arrays (first sub-array, second sub-array, third sub-array, fourth sub-array) arranged in a specific geometric pattern. Each sub-array contains specific current source cells and dummy cells arranged symmetrically. This segmentation allows independent optimization of each sub-array while achieving overall error suppression through their collective geometric relationship, going beyond simple common centroid arrangement.
Solution Approach 2:
The patent introduces dummy cells with specific arrangements that create asymmetric compensation within the otherwise symmetric structure. The dummy cells are positioned to compensate for gradient errors in specific directions, creating a controlled asymmetry that balances the inherent process variations. This controlled asymmetry enhances the error suppression capability while maintaining the overall symmetric layout for matching.
2Manufacturing precision
If oxide film thickness, doping, stress and other parameters vary with chip positions presenting linear gradient change trend, then manufacturing precision is affected, but device complexity increases to compensate
Solution Approach 1:
The patent applies different arrangements of current source cells and dummy cells in different regions (sub-arrays) of the overall array. Each sub-array is optimized for its specific position and gradient direction, with local variations in cell types and dummy cell placements. This local optimization allows the layout to adapt to position-dependent gradient variations without requiring a completely complex redesign of the entire array.
Solution Approach 2:
The patent extends the error suppression from one-dimensional common centroid arrangement to two-dimensional geometric patterns with multiple sub-arrays arranged in specific spatial relationships. By utilizing multiple dimensions (horizontal, vertical, and diagonal arrangements of sub-arrays), the layout can compensate for gradient errors in multiple directions simultaneously, reducing the need for excessive complexity in any single dimension.
3Reliability
If different positions in the chip have different temperatures and power supply voltage drops, then reliability decreases, but manufacturing precision must be maintained
Solution Approach 1:
The patent arranges current source cells and dummy cells in symmetric patterns across multiple sub-arrays positioned at different locations in the chip. This symmetric distribution ensures that cells experiencing similar temperature and voltage drop conditions are balanced by corresponding cells in opposite positions, creating an equipotential-like effect that cancels out position-dependent variations. The geometric symmetry ensures that thermal and voltage gradients affect all sub-arrays equally, maintaining matching accuracy despite environmental variations.
Data Source
AI summary
A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2X−1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2X−1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.