CLB Internal Routing Architecture With Embedded Bnodes for Local FPGA Paths
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Solution Overview
Problem
The reduction in size of transistors and wire size in Field Programmable Gate Array (FPGA) architectures has led to reduced connectivity between interconnect wires and configurable logic block (CLB) input pins, making it less viable to use many interconnect wires across CLB slices, and existing approaches to enhance connectivity are insufficient.
Innovation Solution
A system with a pair of adjacent configurable logic blocks (CLBs) featuring a plurality of inode and bnode structures, where bnodes are embedded in the middle to establish connections between inodes on both sides of the CLBs, enabling localized routing and reducing the need for direct point-to-point connections, and a clock spine and control nodes are moved to the center to improve clocking and reduce horizontal track usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor and wire size are reduced to shrink FPGA size, then device area is reduced, but connectivity between interconnect wires and CLB input pins deteriorates
Solution Approach 1:
The patent introduces inode structures as intermediary elements between the general routing interconnect wires and the CLB input pins. These inodes act as mediation points that enhance connectivity without requiring larger wire sizes or more interconnect tracks, thereby resolving the contradiction between device shrinkage and connectivity maintenance.
2Adaptability or versatility
If CLB size is increased to enhance functionality, then adaptability is improved, but the number of interconnect wires required across CLB slices increases
Solution Approach 1:
The patent merges multiple interconnect wire functions into shared inode structures that serve multiple CLBs. By combining routing resources at the inode level, the system can support larger CLB sizes with enhanced functionality without proportionally increasing the total number of interconnect wires required across CLB slices.
3Speed
If direct point-to-point connections are used between inodes on opposite sides of CLBs, then routing speed is improved, but device complexity and wire usage increase
Solution Approach 1:
The patent introduces a new dimensional approach by embedding bnodes within the CLB structure to create localized routing paths. This internal routing dimension allows signals to travel through the CLB interior rather than requiring external point-to-point connections, achieving fast routing without increasing overall device complexity or wire usage.
Data Source
AI summary
A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.